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a preliminary technical data mixed signal dsp controller with can this information applies to a product under development. its characteristics and specifi- cations are subject to change without notice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. one technology way, p.o.box 9106, norwood, ma 02062-9106, u.s.a. tel:781/329-4700 www.analog.com fax:781/326-8703 ?analog devices,inc., 2002 rev. pra preliminary technical data adsp-21992 mixed signal dsp controller features adsp-219x, 16-bit, fixed point dsp core with up to 160 mips sustained performance 48k words of on chip ram, configured as 32k words on chip 24-bit program ram and 16k words on chip 16-bit data ram external memory interface dedicated memory dma controller for data/instruction transfer between internal/external memory programmable pll and flexible clock generation circuitry enables full speed operation from low speed input clocks ieee jtag standard 1149.1 test access port supports on chip emulation and system debugging 8-channel, 20 msps, 14-bit analog to digital converter system three phase 16-bit center ba sed pwm generation unit with 12.5 ns resolution dedicated 32-bit encoder interface unit with companion encoder event timer dual 16-bit auxiliary pwm outputs 16 general purpose flag i/o pins three programmable 32-bit interval timers spi communications port with master or slave operation synchronous serial communications port (sport) capable of software uart emulation controller area network (can) module fully compliant with v2.0b standard functional block diagram adc control vref pipeline flash adc clock generator / pll pm address/data dm address/data i/o bus 16k x 16 dmram (block 1) 32k x 24 pm ram (block 0) external memory interface (emi) timer 0 timer 1 timer 2 4k x 24 pmrom (block 2) 160 mhz adsp-219x dsp jtag test & emulation address data control i/o registers pwm generation unit encoder interface unit (and eet) auxiliary pwm unit flag i/o spi sport watchdog timer interrupt controller (icntl) por memory dma controller controller area network (can)
for current information contact analog devices at (781) 937-1799 adsp-21992 august 2002 this information applies to a product under development. its characteristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 2 rev. pra preliminary technical data integrated watchdog timer dedicated peripheral interrupt controller with software priority control multiple boot modes precision 1.0v voltage reference integrated power-on-reset (por) generator flexible power management with selectable powerdown and idle modes 2.5v internal operation with 3.3v i/o operating temperature range of ?40oc to +115oc 176 pin lqfp package target applications industrial motor drives un-interruptible power supplies optical networking control data acquisition systems test and measurement systems portable instrumentation general note this data sheet provides pr eliminary information for the adsp-21992 mixed signal digital signal processor. general description the adsp-21992 is a mixed signal dsp controller based on the adsp-219x dsp core, suit able for a variety of high performance industrial motor control and signal process- ing applications that require the combination of a high performance dsp and the mixed signal integration of embedded control peripherals su ch as analog to digital con- version with communications interfaces such as can. the adsp-21992 integrates the 160 mips, fixed point adsp-219x family base architect ure with a serial port, an spi compatible port, a dma controller, three programma- ble timers, general purpose programmable flag pins, extensive interrupt capabilities, on chip program and data memory spaces, and a complete set of embedded control peripherals that permits fast motor control and signal pro- cessing in a highly in tegrated environment. the adsp-21992 architecture is code compatible with previous adsp-217x based admcxxx products. although the architectures are compatible, the adsp-21992, with adsp-219x architecture, has a number of enhancements over earlier architectures. th e enhancements to computa- tional units, data address generators, and program sequencer make the adsp-21992 more flexible and easier to program than the previous adsp-21xx embedded dsps. indirect addressing options pr ovide addressing flexibility? premodify with no update, pre- and post-modify by an immediate 8-bit, two?s comple ment value and base address registers for easier implementa tion of circular buffering. the adsp-21992 integrates 48k words of on chip memory configured as 32k words (24-bit) of program ram, and 16k words (16-bit) of data ram. fabricated in a high speed, lo w power, cmos process, the adsp-21992 operates with a 6. 25 ns instructio n cycle time (160 mips). all instructions, except two multiword instructions, execute in a single dsp cycle. the adsp-21992?s flexible architecture and comprehen- sive instruction set support multiple operations in parallel. for example, in one processo r cycle, the adsp-21992 can: ? generate an address for the next instruction fetch ? fetch the next instruction ? perform one or two data moves ? update one or two data address pointers ? perform a computational operation these operations take pl ace while the processor continues to: ? receive and transmit data through the serial port ? receive or transmit data over the spi port ? access external memory through the external memory interface ? decrement the timers ? operate the embedded contro l peripherals (adc, pwm, eiu, etc.) dsp core architecture ? 6.25 ns instruction cycle time (internal), for up to 160 mips sustained performance ? adsp-218x family code compatible with the same easy to use algebraic syntax ? single cycle instruction execution ? up to 1 mwords of addres sable memory space with twenty four bits of addressing width ? dual purpose program memory for both instruction and data storage ? fully transparent instruction cache allows dual operand fetches in every instruction cycle ? unified memory space permit s flexible address genera- tion, using two independent dag units ? independent alu, multiplier /accumulator, and barrel shifter computational units with dual 40-bit accumulators ? single cycle context switch between two sets of computa- tional and dag registers ? parallel execution of computation and memory instructions ? pipelined architecture supports efficient code execution at speeds up to 160 mips ? register file computations with all non-conditional, non-parallel computational instructions ? powerful program sequencer provides zero overhead looping and conditional instruction execution
this information applies to a product under development. its charac teristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 3 rev. pra for current information contact analog devices at (781) 937-1799 adsp-21992 august 2002 preliminary technical data ? architectural enhancements for compiled c code efficiency ? architecture enhancements beyond adsp-218x family are supported with instruction set extensions for added registers, ports, and peripherals. the clock generator module of the adsp-21992 includes clock control logic that allows the user to select and change the main clock frequency. the module generates two output clocks; the dsp core clock, cclk, and the peripheral clock, hclk. cclk can sustai n clock values of up to 160 mhz, while hclk can be equal to cclk or cclk/2 for values up to a maximum 80mhz peripheral clock. the adsp-21992 instruction se t provides flexible data moves and multifunction (one or two data moves with a computation) instructions. ev ery single word instruction can be executed in a sing le processor cycle. the adsp-21992 assembly language uses an algebraic syntax for ease of coding and readab ility. a comprehensive set of development tools supports program development. the block diagram figure 1 shows the architecture of the embedded adsp-219x core. it contains three independent computational units: the alu, the multiplier/accumulator (mac), and the shifter. the computational units process 16-bit data from the register file and have provisions to support multiprecision comp utations. the alu performs a standard set of arithmetic and logic operations; division primitives are also supported. the mac performs single cycle multiply, multiply/add, and multiply/subtract opera- tions. the mac has two 40-bit accumulators, which help with overflow. the shifter perf orms logical and arithmetic shifts, normalization, denormalization, and derive exponent operations. the shifter can be used to efficiently implement numeric format control, including multiword and block floating point representations. register usage rules influe nce placement of input and results within the computational units. for most operations, the computational units? data registers act as a data register file, permitting any input or re sult register to provide input to any unit for a computation. for feedback operations, the computational units let the output (result) of any unit be figure 1. adsp-21992 dsp block diagram i/o registers (memory mapped) control status buffers i/o processor interrupt controller/ timers/flags cache 64 x 24-bit jtag test & emulation addr bus mux external memory interface external port data bus mux pm address bus dm address bus pm data bus dm data bus bus connect (px) adsp-219x dsp core program sequencer data register file mult barrel shifter alu dma controller input registers result registers 16 x 16-bit ahb core interface dag1 4x4x16 dag2 4x4x16 data data address two independent blocks internal sram address dma data dma address embedded control peripherals and communications ports
for current information contact analog devices at (781) 937-1799 adsp-21992 august 2002 this information applies to a product under development. its characteristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 4 rev. pra preliminary technical data input to any unit on the next cycle. for cond itional or mul- tifunction instructions, there ar e restrictions on which data registers may provide inputs or receive results from each computational unit. for more information, see the adsp-219x dsp instruction set reference . a powerful program sequencer co ntrols the flow of instruc- tion execution. the sequencer supports conditional jumps, subroutine calls, and low interrupt overhead. with internal loop counters and loop st acks, the adsp-21992 executes looped code with zero overhe ad; no explicit jump instruc- tions are required to maintain loops. two data address generators (dags) provide addresses for simultaneous dual operand fetches (from data memory and program memory). each dag maintains and updates four 16-bit address pointe rs. whenever the pointer is used to access data (indirect ad dressing), it is pr e- or post-modified by the value of one of four possible modify registers. a length value and base address may be associated with each pointer to implement automatic modulo addressing for circular buffers. page registers in the dags allow circular addressing within 64k word bo undaries of each of the 256 memory pages, but these buffers may not cross page boundaries. secondary registers duplicate al l the primary registers in the dags; switching between primary and secondary registers provides a fast context switch. efficient data transfer in the co re is achieved with the use of internal buses: ? program memory address (pma) bus ? program memory data (pmd) bus ? data memory address (dma) bus ? data memory data (dmd) bus ? direct memory a ccess address bus ? direct memory access data bus the two address buses (pma and dma) share a single external address bus, allowing memory to be expanded off chip, and the two data buses (pmd and dmd) share a single external data bus. boot memory space and i/o memory space also share the external buses. program memory can store both instructions and data, per- mitting the adsp-21992 to fetch two operands in a single cycle, one from program memory and one from data memory. the dsp?s dual memory buses also let the embedded adsp-219x core fe tch an operand from data memory and the next instruction from program memory in a single cycle. memory architecture the adsp-21992 provides 48k words of on chip sram memory. this memory is divided into two blocks; a 32k x 24-bit (block 0) and a 16k x 16- bit (block 1). in addition, the adsp-21992 provides a 4k x 24-bit block of program memory boot rom (that is reserved by adi for boot load routines). the memory map of the adsp-21992 is illus- trated in figure 2. as shown in figure 2, the two internal memory ram blocks reside in memory page 0. the entire dsp memory map consists of 256 pages (pages 0 to 255), and each page is 64 kwords long. external memory space consists of four memory banks (banks 0-3) and supports a wide variety of memory devices. each bank is selectable using unique memory select lines (ms3 - ms0 ) and has configurable page boundaries, wait states, and wa it state modes. the 4k words of on chip boot rom populate s the top of page 255, while the remaining 254 pages are addressable o ff chip. i/o memor y pages differ from external memor y in that they are 1k word long, and the external i/o pages have their own select pin (ioms ). pages 0-31 of i/o memory space reside on chip and contai n the configuration registers for the peripherals. both the adsp _219x core and dma capable peripherals can access the dsp?s entire memory map. note: the physical external memory addresses are limited by 20 address lines, and are determined by the external data width and packing of the ex ternal memory space. the strobe signals (ms3 - 0) can be programmed to allow the user to change starting pa ge addresses at run time. internal (on chip) memory the adsp-21992?s unified program and data memory space consists of 16m location s that are accessible through two 24-bit address buses, the pma and dma buses. the figure 2. adsp-21992 dsp core memory map at reset 0x000000 0x00 7fff 0x00 bfff 0x01 0000 0x40 0000 0x80 0000 0xc0 0000 0xff 0000 0xff 1000 0xff ffff 0x00 8000 0x00 c000 0x00 ffff 0xff 0fff page 0 (64k) on-chip (0 wait state) external memory (4m - 64k) pages 1 to 63 bank 0 (off-chip) ms0 page 255 (on-chip external memory external memory pages 64 to 127 bank 1 (off-chip) pages 128 to 191 bank 2 (off-chip) pages 192 to 254 bank 0 (off-chip) ms1 ms2 ms3 external memory (4m - 64k) block 0: 32k x 24-bit ram reserved (16k) block 1: 16k x 16-bit ram block 2: 4k x 24-bit pm rom unused on-chip memory (60k)
this information applies to a product under development. its charac teristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 5 rev. pra for current information contact analog devices at (781) 937-1799 adsp-21992 august 2002 preliminary technical data dsp uses slightly different mechanisms to generate a 24-bit address for each bus. the ds p has three functions that support access to th e full memory map. ? the dags generate 24-bit addresses for data fetches from the entire dsp memory address range. because dag index (address) registers are 16 bits wide and hold the lower 16 bits of the address, each of the dags has its own 8-bit page register (dmpgx) to hold the most significant eight address bits. before a dag generates an address, the program must set the dag?s dmpgx register to the appropriate memory page. the dmpg1 register is also used as a page register when accessing external memory. the program must set dm pg1 accordingly, when accessing data variables in external memory. a 'c' program macro is provided for setting this register. ? the program sequencer generates the addresses for instruction fetches. for relative addressing instructions, the program sequencer bases addresses for relative jumps, calls, and loops on the 24-bit program counter (pc). in direct addressing in structions (two word instructions), the instruction provides an immediate 24-bit address value. the pc allows linear ad dressing of the full 24-bit address range. ? for indirect jumps and ca lls that use a 16-bit dag address register for part of the branch address, the program sequencer relies on an 8-bit indirect jump page (ijpg) register to supply the most significant eight address bits. before a cross pa ge jump or call, the program must set the program sequencer ?s ijpg register to the appropriate memory page. the adsp-21992 has 4k word of on chip rom that holds boot routines. the dsp starts executing instru ctions from the on chip boot rom, which starts the boot process. for more information, see booting modes on page 14. the on chip boot rom is located on page 255 in the dsp?s memory space map, starti ng at address 0xff0000. external (off chip) memory each of the adsp-21992?s off chip memory spaces has a separate control register, so applications can configure unique access parameters for each space. the access param- eters include read and writ e wait counts, wait state completion mode, i/o clock divide ratio, write hold time extension, strobe polarity, and data bus width. the core clock and peripheral clock ra tios influence the external memory access strobe widths. for more information, see clock signals on page 13. the off chip memory spaces are: ? external memory space (ms3?0 pins) ? i/o memory space (ioms pin) ? boot memory space (bms pin) all of these off chip memory spaces are accessible through the external port, which can be configured for 8-bit or 16-bit data widths. external memory space external memory space consis ts of four memory banks. these banks can contain a co nfigurable number of 64 k word pages. at reset, the pa ge boundaries for external memory have bank0 containing pages 1 to 63, bank1 con- taining pages 64 to 127, bank2 containing pages 128 to 191, and bank3 contai ning pages 192 to 254. the ms3 -ms0 memory bank pins select ban ks 3-0, respectively. both the adsp-219x core an d dma capable peripherals can access the dsp?s external memory space. all accesses to external memory are managed by the external memory interface unit (emi). i/o memory space the adsp-21992 supports an ad ditional external memory called i/o memory space. th e io space consists of 256 pages, each containing 1024 addresses. this space is designed to support simple co nnections to peripherals (such as data converters and external registers) or to bus interface asic data registers. the first 32k addresses (io pages 0 to 31) are reserved for on chip peripherals. the upper 224k addresses (io pages 32 to 255) are available for external peripheral devices. external i/o pages have their own select pin (ioms ). the dsp instruction se t provides instructions for accessing i/o space. boot memory space boot memory space consists of one off chip bank with 254 pages. the bms memory bank pin selects boot memory space. both the adsp-219x co re and dma capable periph- figure 3. adsp-21992 i/o memory map on-chip peripherals 16-bits off-chip peripherals 16-bits pages 0 to 31 1024 words/page 2 peripherals/page 0x00::0x000 0x20::0x000 0xff::0x3ff 0x1f::0x3ff pages 32 to 255 1024 words/page
for current information contact analog devices at (781) 937-1799 adsp-21992 august 2002 this information applies to a product under development. its characteristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 6 rev. pra preliminary technical data erals can access the dsp?s off ch ip boot memory space. after reset, the dsp always starts ex ecuting instruct ions from the on chip boot rom. bus request and bus grant the adsp-21992 can relinquish control of the data and address buses to an external device. when the external device requires access to the bu s, it asserts the bus request (br ) signal. the (br ) signal is arbitrated with core and peripheral requests. external bus requests have the lowest priority. if no other internal request is pending, the external bus request will be granted. due to synchronizer and arbi- tration delays, bus grants will be provided with a minimum of three peripheral clock delays. the adsp-21992 will respond to the bus grant by: ? three stating the data and address buses and the ms3?0 , bms , ioms , rd , and wr output drivers. ? asserting the bus grant (bg ) signal. the adsp-21992 will halt progra m execution if the bus is granted to an external device and an instruction fetch or data read/write request is made to external general purpose or peripheral memory spaces. if an instruction requires two external memory read accesses, the bus will not be granted between the two accesses. if an instruction requires an external memory read and an external memory write access, the bus may be granted between the two accesses. the external memory interface can be configured so that the core will have exclusive use of the interface. dma and bus requests will be granted. when the external device releases br , the dsp releases bg and continues pr ogram execution from the point at which it stopped. the bus request feature operates at all times, even while the dsp is booting and reset is active. the adsp-21992 asserts the bgh pin when it is ready to start another external port a ccess, but is held off because the bus was previously grante d. this mechanism can be extended to define more comp lex arbitration protocols for implementing more elabor ate multimaster systems. dma controller the adsp-21992 has a dma controller that supports automated data transfers with minimal overhead for the dsp core. cycle stealing dma transfers can occur between the adsp-21992?s internal me mory and any of its dma capable peripherals. addition ally, dma transfers can be accomplished between any of the dma capable peripherals and external devices connected to the external memory interface. dma capable peripherals include the sport and spi ports, and adc control module. each individual dma capable peripheral has a dedicated dma channel. to describe each dma sequence, the dma controller uses a set of parameters?called a dma descriptor. when succes- sive dma sequences are need ed, these dma descriptors can be linked or chained togeth er, so the completion of one dma sequence auto initiates an d starts the next sequence. dma sequences do not contend for bus access with the dsp core, instead dmas ?steal? cycles to access memory. all dma transfers use the dma bus shown in figure 1 on page 3 . because all of the periph erals use the same bus, arbitration for dma bus access is needed. the arbitration for dma bus access appears in table 1 . dsp peripherals architecture the adsp-21992 contains a number of special purpose, embedded control peripherals, which can be seen in the functional block diagram on page 1. the adsp-21992 contains a high performan ce, 8-channel, 14-bit adc system with dual channel simultaneous sampling ability across 4 pairs of inputs. an internal precision voltage reference is also available as part of the adc system. in addition, a three phase, 16-bi t, center based pwm genera- tion unit can be used to pro duce high accuracy pwm signals with minimal processor over head. the adsp-21992 also contains a flexible incrementa l encoder interface unit for position sensor feedback; two adjustable frequency auxiliary pwm outputs, 16 lines of digital i/o; a 16-bit watchdog timer; three general purpose timers and an interrupt con- troller that manages all peripheral interrupts. finally, the adsp-21992 contains an integr ated power-on-reset (por) circuit that can be used to gene rate the required reset signal for the device on power-on. the adsp-21992 has an external memory interface that is shared by the dsp?s core, the dma controller, and dma capable peripherals, which include the adc, sport, and spi communication ports. the ex ternal port consists of a 16-bit data bus, a 20-bit address bus, and control signals. figure 4. adsp-21992 boot memory map pages 1 to 254 64k words/page 0 x 0 1 0 0 0 0 0xfe 0000 off-chip boot memory 16-bits table 1. i/o bus arbitration priority dma bus master arbitration priority sport receive dma 0?highest sport transmit dma 1 adc control dma 2 spi0 receive/transmit dma 3 memory dma 4?lowest
this information applies to a product under development. its charac teristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 7 rev. pra for current information contact analog devices at (781) 937-1799 adsp-21992 august 2002 preliminary technical data the data bus is configurable to provide an 8 or 16 bit interface to external memory. support for word packing lets the dsp access 16- or 24-bit wo rds from external memory regardless of the external data bus width. the memory dma controller lets the adsp-21992 move data and instructions from between memory spaces: inter- nal-to-external, internal-to-internal, and external-to- external. on chip peripherals ca n also use this controller for dma transfers. the embedded adsp-219x core can respond to up to seventeen interrupts at any given time: three internal (stack, emulator kernel, and power down), two external (emulator and reset), and twelve user defined (peripherals) interrupts. programmers assign each of the 32 peripheral interrupt requests to one of the 12 us er defined interrupts. these assignments determine the priori ty of each peripheral for interrupt service. the following sections provide a functional overview of the adsp-21992 peripherals. serial peripheral interface (spi) port the serial peripheral interface (spi) port provides func- tionality for a generic configurable serial port interface based on the spi standard, wh ich enables the dsp to com- municate with multiple sp i compatible devices. key features of the spi port are: ? interface to host microcontroller or serial eeprom ? master or slave operation (3 wire interface miso, mosi, sck) ? data rates to 20 mbaud (16-bit baud rate selector) ? 8 or 16-bit transfer ? programmable clock phase & polarity ? broadcast mode - 1 master, multiple slaves ? dma capability & dedicated interrupts ? pf0 can be used as sl ave select input line ? pf1-pf7 can be used as ex ternal slave select output spi is a 3 wire interface cons isting of 2 data pins (mosi and miso), one clock pin (sck), and a single slave select input (spiss0) that is multiplexed with the pf0 flag io line and seven slave select outputs (spisel1 to spisel7) that are multiplexed with the pf1 to pf7 flag io lines. the spiss0 input is used to se lect the adsp-21992 as a slave to an external master. the spisel1 to spisel7 outputs can be used by the adsp- 21992 (acting as a master) to select/enable up to seven extern al slaves in an multi device spi configuration. in a multimaster or a multi device con- figuration, all mosi pins are tied together, all miso pins are tied together, and all sc k pins are tied together. during transfers, the spi port simultaneously transmits and receives by serially shifting data in and out on the serial data line. the serial clock line synchronizes the shifting and sampling of data on the serial data line. in master mode, the dsp?s co re performs the following sequence to set up and initiate spi transfers: 1. enables and configures the spi port operation (data size, and transfer format). 2. selects the target spi slave with the spiselx output pin (reconfigured programmable flag pin). 3. defines one or more dma descriptors in page 0 of i/o memory space (optional in dma mode only). 4. enables the spi dma engine and specifies transfer direction (optional in dma mode only). 5. in non dma mode only, reads or writes the spi port receive or transmit data buffer. the sck line generates the pr ogrammed clock pulses for simultaneously shifting data out on mosi and shifting data in on miso. in dma mode only, transfers continue until the spi dma word count transitions from 1 to 0. in slave mode, the dsp core performs the following sequence to set up the spi port to receive data from a master transmitter: 1. enables and configures the spi slave port to match the operation parameters set up on the master (data size and transfer format) spi transmitter. 2. defines and generates a receive dma descriptor in page 0 of memory space to interrupt at the end of the data transfer (optional in dma mode only). 3. enables the spi dma engine for a receive access (optional in dma mode only). 4. starts receiving the data on the appropriate sck edges after receiving an spi chip select on the spiss0 input pin (reconfigured programmable flag pin) from a master in dma mode only, reception continues until the spi dma word count transitions from 1 to 0. the dsp core could continue, by queuing up the next dma descriptor. a slave mode transmit operatio n is similar, except the dsp core specifies the data buffer in memory space from which to transmit data, generates and relinquishes control of the transmit dma descriptor, and begins filling the spi port data buffer. if the spi controller is not ready on time to transmit, it can transmit a ?zero? word. dsp serial port (sport) the adsp-21992 incorporates a complete synchronous serial port (sport) for serial and multiprocessor commu- nications. the sport suppor ts the following features: ? bidirectional: the sport has independent transmit and receive sections. ? double buffered: the sport section (both receive and transmit) has a data register for transferring data words to and from other parts of the processor and a register for shifting data in or out. the double buffering provides additional time to service the sport.
for current information contact analog devices at (781) 937-1799 adsp-21992 august 2002 this information applies to a product under development. its characteristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 8 rev. pra preliminary technical data ? clocking: the sport can use an external serial clock or generate its own in a wide range of frequencies down to 0 hz. maximum clock value is 40 mhz for internally generated clock. ? word length: each sport sect ion supports serial data word lengths from three to si xteen bits that can be trans- ferred either msb first or lsb first. ? framing: each sport sectio n (receive and transmit) can operate with or without frame synchronization signals for each data word; with internally generated or externally generated frame signals; with active high or active low frame signals; with either of two pulse widths and frame signal timing. ? companding in hardware: each sport section can perform a law and law companding according to ccitt recommendation g.711. ? direct memory access with si ngle cycle overhead: using the built in dma master, th e sport can automatically receive and/or transmit multip le memory buffers of data with an overhead of only one dsp cycle per data word. the on chip dsp via a link ed list of memory space resident dma descriptor blocks can configure transfers between the sport and memory space. this chained list can be dynamically allocated and updated. ? interrupts: each sport sect ion (receive and transmit) generates an interrupt upon completing a data word transfer, or after transferring an entire buffer or buffers if dma is used. ? multi channel capability: the sport can receive and transmit data selectively from channels of a serial bit stream that is time division multiplexed into up to 128 channels. this is especially us eful for t1 interfaces or as a network communication scheme for multiple proces- sors. the sports also support t1 and e1 carrier systems. ? each sport channel (tx and rx) supports a dma buffer of up to 8, 16-bit transfers. ? the sport operates at a freq uency of up to ? the clock frequency of the hclk ? the sport is capable of uart software emulation. controller area network (can) module the adsp-21992 contains a controller area network (can) module. key features of the can module are: ? conforms to the can v2.0b standard. ? supports both standard (11- bit) and extended (29-bit) identifiers ? supports data rates of up to 1mbit/sec (and higher) ? 16 configurable mailboxes (a ll receive or transmit) ? dedicated acceptance ma sk for each mailbox ? data filtering (first 2 bytes) can be used for acceptance filtering ? error status and warning registers ? transmit priority by identifier ? universal counter module ? readable receive and transmit counters the can module is a low baud rate serial interface intended for use in applicat ions where baud rates are typically under 1 mbit/ sec. th e can protocol incorporates a data crc check, message error tracking and fault node confinement as means to improve network reliability to the level required for control applications. the can module architecture is based around a 16-entry mailbox ram. the mailbox is accessed sequentially by the can serial interface or th e host cpu. each mailbox consists of eight 16-bit data words. the data is divided into fields, which includes a messag e identifier, a time stamp, a byte count, up to 8 bytes of data, and several control bits. each node monitors the mess ages being passed on the network. if the identifier in the transmitted message matches an identifier in one of it's mailboxes, then the module knows that the message was meant for it, passes the data into it's appropriate mailbox, and signals the host of its arrival with an interrupt. the can network itself is a single, differential pair line. all nodes continuously monitor this line. there is no clock wire. messages are passed in one of 4 standard message types or frames. synchronization is achi eved by an elaborate sync scheme performed in each ca n receiver. message arbitra- tion is accomplished 1 bit at a time. a dominant polarity is established for the network. all nodes are allowed to start transmitting at the same time following a frame sync pulse. as each node transmit s a bit, it checks to see if the bus is the same state that it transmitted. if it is, it continues to transmit. if not, then another node has transmitted a dominant bit so the first node knows it has lost the arbitra- tion and it stops transmitting. the arbitration continues, bit by bit until only 1 node is left transmitting. the electrical characteristics of each network connection are very stringent so the can interface is typically divided into 2 parts: a controller and a transceiver. this allows a single controller to support different drivers and can networks. the adsp-21992 can module represents only the controller part of the inte rface. this module's network i/o is a single transmit line a nd a single receive line, which communicate to a line transceiver. analog to digital conversion system the adsp-21992 contains a fast , high accuracy, multiple input analog to digital conversi on system with simultaneous sampling capabilities. this a/ d conversion system permits
this information applies to a product under development. its charac teristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 9 rev. pra for current information contact analog devices at (781) 937-1799 adsp-21992 august 2002 preliminary technical data the fast, accurate conversion of analog signals needed in high performance embedded sy stems. key features of the adc system are: ? 14-bit pipeline (6-stage pipeline) flash analog to digital converter. ? 8 dedicated analog inputs. ? dual channel simultaneous sampling capability. ? programmable adc clock rate to maximum of 20 msps. ? first channel adc data valid approximately 400 ns after convst (at 20 msps). ? all 8 inputs converted in approximately 800 ns (at 20 msps). ? 2.0 v peak to peak input voltage range. ? multiple convert start sources. ? internal or external voltage reference. ? out of range detection. ? dma capable transfers from adc to memory. the adc system is based on a pipeline flash converter core, and contains dual input sample and hold amplifiers so that simultaneous sampling of two input signals is supported. the adc system provides an an alog input voltage range of 2.0vpp and provides 14-bit performance with a clock rate of up to 20 mhz. the adc sy stem can be programmed to operate at a clock rate that is programmable from hclk ? 4 to hclk ? 30, to a maximum of 20 mhz. the adc input structure supp orts 8 independent analog inputs; 4 of which are multiplexed into one sample and hold amplifier (a_sha) and 4 of wh ich are multiplexed into the other sample and hold amplifier (b_sha). at the 20 mhz hclk rate, the first data value is valid approximately 400 ns after the convert start command. all 8 channels are converted in approximately 800 ns. the core of theadsp-21992 prov ides 14-bit data such that the stored data values in the adc data registers are 14-bits wide. voltage reference the adsp-21992 contains an on board band gap reference that can be used to provide a precise 1.0v output for use by the a/d system and externally on the vref pin for biasing and level shifting functions. additionally, the adsp-21992 may be configured to operate with an external reference applied to the vref pin, if required. pwm generation unit key features of the three phase pwm generation unit are: ? 16-bit, center based pwm generation unit ? programmable pwm pulsewidth, with resolutions to 12.5 ns (at 80 mhz) ? single/double update modes ? programmable dead time and switching frequency ? two's complement implementation permits smooth transition into full on and full off states ? possibility to synchronize the pwm generation to an external synchronization ? special provisions for bdcm operation (crossover and output enable functions) ? wide variety of special switched reluctance (sr) operating modes ? output polarity and clock gating control ? dedicated asynchronous pwm shutdown signal ? multiple shut down sources, independently for each unit the adsp-21992 integrates a flexible and programmable, three phase pwm waveform generator that can be pro- grammed to generate the requ ired switching patterns to drive a three phase voltage source inverter for ac induction (acim) or permanent magnet synchronous (pmsm) motor control. in ad dition, the pwm bloc k contains special functions that considerably simplify the generation of the required pwm switching patter ns for control of the elec- tronically commutated motor (ecm) or brushless dc motor (bdcm). tying a dedicated pin, pwmsr , to gnd, enables a special mode, for switched reluctance motors (srm). the six pwm output signals cons ist of three high side drive pins (ah, bh and ch) and three low side drive signals pins (al, bl and cl). the polarity of the generated pwm signals may be set via hardware by the pwmpol input pin, so that either active hi or active lo pwm patterns can be produced. the switching frequency of the generated pwm patterns is programmable using the 16-bit pwmtm register. the pwm generator is capable of operating in two distinct modes, single update mode or double update mode. in single update mode the duty cycle values are programmable only once per pwm period, so that the resultant pwm patterns are symmetrical abou t the midpoint of the pwm period. in the double update mode, a second updating of the pwm registers is implemen ted at the midpoint of the pwm period. in this mode, it is possible to produce asym- metrical pwm patterns. that produce lower harmonic distortion in three phase pwm inverters. auxiliary pwm generation unit key features of the auxiliary pwm generation unit are: ? 16-bit, programmable frequency, programmable duty cycle pwm outputs ? independent or offset operating modes ? double buffered control of duty cycle and period registers
for current information contact analog devices at (781) 937-1799 adsp-21992 august 2002 this information applies to a product under development. its characteristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 10 rev. pra preliminary technical data ? separate auxiliary pwm synchronization signal and asso- ciated interrupt (can be used to trigger adc convert start). ? separate auxiliary pwm shutdown signal (auxtrip ). the adsp-21992 integrates a two channel, 16-bit, auxiliary pwm output unit that can be programmed with variable frequency, variable duty cycle values and may operate in two different modes, independent mode or offset mode. in independent mode, the two auxiliary pwm gen- erators are completely indepe ndent and separate switching frequencies and duty cycles may be programmed for each auxiliary pwm output. in offset mode the switching frequency of the two signals on the aux0 and aux1 pins is identical. bit 4 of the auxctrl register places the auxiliary pwm channel pair in independent or offset mode the auxiliary pwm generation unit provides two chip output pins, aux0 and aux1 (on which the switching signals appear) and one chip input pin, auxtrip , which can be used to shutdown the switching signals, for example in a fault condition. encoder interface unit the adsp-21992 incorporat es a powerful encoder interface block to incremental shaft encoders that are often used for position feedback in high performance motion control systems. ? quadrature rates to 53 mh z (at 80 mhz peripheral clock). ? programmable filtering of all encoder input signals ? 32-bit encoder counter ? variety of hardware and software reset modes ? two registration inputs to latch eiu count value with corresponding registration interrupt ? status of a/b signals latched with reading of eiu count value. ? alternative frequency & direction mode ? single north marker mode ? count error monitor function with dedicated error interrupt ? dedicated 16-bit loop timer with dedicated interrupt ? companion enco der event (1 ? t) timer unit. the encoder interface unit (e iu) includes a 32-bit quadra- ture up/down counter, programmable input noise filtering of the encoder input signals and the zero markers, and has four dedicated chip pins. th e quadrature encoder signals are applied at the eia and eib pins. alternatively, a frequency and direction set of inputs may be applied to the eia and eib pins. in addition, two north marker/strobe inputs are provided on pins eiz and eis. these inputs may be used to latch the contents of the encoder quadrature counter into dedicated registers, eizlatch and eislatch, on the occurrence of external events at the eiz and eis pins. these events may be programmed to be either rising edge only (latch event) or rising edge if the encoder is moving in the forward direct ion and falling edge if the encoder is moving in the reve rse direction (software latched north marker functionality). the encoder interface unit incorporates programmable noise filtering on the four enco der inputs to prevent spurious noise pulses from adversely af fecting the operation of the quadrature counter. the encode r interface unit operates at a clock frequency equal to the hclk rate. the encoder interface unit operates correctly with encoder signals at fre- quencies of up to 13.25 mhz, corresponding to a maximum quadrature frequency of 53 mhz (assuming an ideal quadrature relationship be tween the input eia and eib signals). the eiu may be programmed to use the north marker on eiz to reset the quadrature encoder in hardware, if required. alternatively, the north marker can be ignored, and the encoder quadrature counter is reset according to the contents of a maximum co unt register, eiumaxcnt. there is also a ?single north marker? mode available in which the encoder quadrature co unter is reset only on the first north marker pulse. the encoder interface unit can also be made to implement some error checking functions. if an encoder count error is detected (due to a disconnect ed encoder line, for example), a status bit in the eiustat register is set, and an eiu count error interrupt is generated. the encoder interface unit of the adsp-21992 contains a 16-bit loop timer that consists of a timer register, period register and scale register so that it can be programmed to time out and reload at appropriate intervals. when this loop timer times out, an eiu loop timer timeout interrupt is generated. this interrupt could be used to control the timing of speed and position control loops in high perfor- mance drives. the encoder interface unit also includes a high performance encoder event timer (eet) block that permits the accurate timing of successive events of the encoder inputs. the eet can be programmed to time th e duration between up to 255 encoder pulses and can be used to enhance velocity estima- tion, particularly at low speeds of rotation. flag i/o (fio) peripheral unit the fio module is a generic parallel i/o interface that supports sixteen bidi rectional multifunction flags or general purpose digital i/o signals (pf15-pf0). all sixteen flag bits can be in dividually configured as an input or output based on the content of the direction (dir) register, and can also be used as an interrupt source for one of two fio interrupts. when co nfigured as input, the input
this information applies to a product under development. its charac teristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 11 rev. pra for current information contact analog devices at (781) 937-1799 adsp-21992 august 2002 preliminary technical data signal can be programmed to se t the flag on either a level (level sensitive input/interrupt ) or an edge (edge sensitive input/interrupt). the fio module can also be us ed to generate an asynchro- nous unregistered wake up signal fio_wakeup for dsp core wake up after power down. the fio lines, pf7 - pf1 can also be configured as external slave select outputs for the spi communications port, while pf0 can be configured to act as a slave select input. the fio lines can be configured to act as a pwm shutdown source for the three phase pw m generation unit of the adsp-21992. watchdog timer the adsp-21992 integrates a wa tchdog timer that can be used as a protection mechan ism against unintentional software events. it can be used to cause a complete dsp and peripheral reset in such an event. the watchdog timer consists of a 16-bit timer that is clocked at the external clock rate (clkin or crystal input frequency). in order to prevent an unwanted timeout or reset, it is necessary to periodically write to the watchdog timer register. during abnormal system operation, the watchdog count will eventually decr ement to 0 and a watchdog timeout will occur. in the system, the watchdog timeout will cause a full reset of the dsp core and peripherals. general purpose timers the adsp-21992 contains a ge neral purpose timer unit that contains three identica l 32-bit timers. the three pro- grammable interval timers (timer0, timer1 and timer2) generate periodic interrupts. each timer can be indepen- dently set to operate in one of three modes: ? pulse waveform generation (pwm_out) mode ? pulse width count/capture (wdth_cap) mode ? external event watchdog (ext_clk) mode each timer has one bidirectio nal chip pin, tmr2-tmr0. for each timer, the a ssociated pin is config ured as an output pin in pwm_out mode and as input pin in wdth_cap and ext_clk modes. interrupts the interrupt controller lets the dsp respond to 17 inter- rupts with minimum overhead . the dsp core implements an interrupt priority scheme as shown in table 2 . applica- tions can use the unassigned slots for software and peripheral interrupts. the peripheral interrupt controller is used to assign the various peripheral interrupts to the 12 user assignable interrupts of the dsp core. there is no assigned priority for the peripheral interrupts after reset. to assign the peripheral interrupts a different priority, applications write the new priority to their corre- sponding control bits (deter mined by their id) in the interrupt priority control register. interrupt routines can either be nested with higher priority interrupts taking precedence or processed sequentially. interrupts can be masked or unmasked with the imask register. individual interrupt requests are logically anded with the bits in imask; the highest priority unmasked interrupt is then selected. th e emulation, power down, and reset interrupts are nonmaskabl e with the imask register, but software can use the dis int instruction to mask the power down interrupt. table 2. interrupt priorities/addresses interrupt imask/ irptl vector address emulator (nmi) ?highest priority na na reset (nmi) 0 0x00 0000 power down (nmi) 1 0x00 0020 loop and pc stack 2 0x00 0040 emulation kernel 3 0x00 0060 user assigned interrupt (usr0) 4 0x00 0080 user assigned interrupt (usr1) 5 0x00 00a0 user assigned interrupt (usr2) 6 0x00 00c0 user assigned interrupt (usr3) 7 0x00 00e0 user assigned interrupt (usr4) 8 0x00 0100 user assigned interrupt (usr5) 9 0x00 0120 user assigned interrupt (usr6) 10 0x00 0140 user assigned interrupt (usr7) 11 0x00 0160 user assigned interrupt (usr8) 12 0x00 0180 user assigned interrupt (usr9) 13 0x00 01a0 user assigned interrupt (usr10) 14 0x00 01c0 user assigned interrupt (usr11) ?lowest priority 15 0x00 01e0
for current information contact analog devices at (781) 937-1799 adsp-21992 august 2002 this information applies to a product under development. its characteristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 12 rev. pra preliminary technical data the interrupt control (icntl) register controls interrupt nesting and enables or disables interrupts globally. the irptl register is used to force and clear interrupts. on chip stacks preserve the processor status and are auto- matically maintained during interrupt handling. to support interrupt, loop, and subroutine nesting, the pc stack is 33 levels deep, the loop stack is eight levels deep, and the status stack is 16 levels deep. to prevent stack overflow, the pc stack can generate a stack level interrupt if the pc stack falls below three locations full or rises above 28 locations full. the following instructions globally enable or disable interrupt servicing, regardless of the state of imask. ena int; dis int; at reset, interrupt servicing is disabled. for quick servicing of interrupts, a secondary set of dag and computational registers ex ist. switching between the primary and secondary registers lets programs quickly service interrupts, while preserving the state of the dsp. peripheral interrupt controller the peripheral interrupt controller is a dedicated periph- eral unit of the adsp-21992 (accessed via io mapped registers). the function of th e peripheral interrupt control- ler is to manage the connect ion of up to 32 peripheral interrupt requests to the dsp core. for each peripheral interrupt so urce, there is a unique 4-bit code that allows the user to as sign the particular peripheral interrupt to any one of the 12 us er assignable interrupts of the embedded adsp-219x core. therefore, the peripheral interrupt controller of the ad sp-21992 contains 8, 16-bit interrupt priority registers (interrupt priority register 0 (ipr0) to interrupt priority register 7 (ipr7)). each interrupt priority register contains a four 4-bit codes; one specifically assigned to ea ch peripheral interrupt. the user may write a value between 0x0 and 0xb to each 4-bit location in order to effect ively connect the particular interrupt source to the corr esponding user assignable interrupt of the adsp-219x core. writing a value of 0x0 connects the peripheral interrupt to the usr0 user assignable inte rrupt of the adsp-219x core while writing a value of 0x b connects the peripheral interrupt to the usr11 user as signable interrupt. the core interrupt usr0 is the highest priority user interrupt, while usr11 is the lowest priority. writing a value between 0xc and 0xf effectively disables th e peripheral interrupt by not connecting it to any adsp-219 x core interrupt input. the user may assign more than one peripheral interrupt to any given adsp-219x core interrupt. in that case, the onus is on the user software in th e interrupt vector table to determine the exact interrupt source through reading status bits etc. this scheme permits the user to assign the number of specific interrupts that are uniq ue to their application to the interrupt scheme of the adsp- 219x core. the user can then use the existing interrupt prio rity control scheme to dynam- ically control the priorities of the 12 core interrupts. low power operation the adsp-21992 has four low power options that signifi- cantly reduce the power dissipation when the device operates under standby condit ions. to enter any of these modes, the dsp executes an idle instruction. the adsp-21992 uses the configuration of the pd, stck, and stall bits in the pllctl register to select between the low power modes as the dsp ex ecutes the idle instruction. depending on the mode, an idle shuts off clocks to different parts of the dsp in the different modes. the low power modes are: ? idle ? power down core ? power down core/peripherals ? power down all idle mode when the adsp-21992 is in idle mode, the dsp core stops executing instru ctions, retains the cont ents of the instruc- tion pipeline, and waits for an interrupt. the core clock and peripheral clock continue running. to enter idle mode, the dsp can execute the idle instruc- tion anywhere in code. to exit idle mode, the dsp responds to an interrupt and (after two cycles of latency) resumes executing in structions. power down core mode when the adsp-21992 is in power down core mode, the dsp core clock is off, but the dsp retains the contents of the pipeline and keeps the pll running. the peripheral bus keeps running, letting the peripherals receive data. to exit power down core mode, the dsp responds to an interrupt and (after two cycles of latency) resumes executing instructions. power down core/peripherals mode when the adsp-21992 is in power down core/peripherals mode, the dsp core clock and peripheral bus clock are off, but the dsp keeps the pll ru nning. the dsp does not retain the contents of the in struction pipeline.the periph- eral bus is stopped, so the peripherals cannot receive data. to exit power down core/peripherals mode, the dsp responds to an interrupt and (after five to six cycles of latency) resumes executing instructions.
this information applies to a product under development. its charac teristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 13 rev. pra for current information contact analog devices at (781) 937-1799 adsp-21992 august 2002 preliminary technical data power down all mode when the adsp-21992 is in power down all mode, the dsp core clock, the peripheral clock, and the pll are all stopped. the dsp does not re tain the contents of the instruction pipeline. the peripheral bus is stopped, so the peripherals cannot receive data. to exit power down core/peripherals mode, the dsp responds to an interrupt and (after 500 cycles to re-stabilize the pll) resumes executing instructions. clock signals the adsp-21992 can be clocked by a crystal oscillator or a buffered, shaped clock deri ved from an external clock oscillator. if a crystal oscillator is used, the cr ystal should be connected across the clkin and xtal pins, with two capacitors connected as shown in figure 5 . capacitor values are dependent on crystal type and should be specified by the crystal manufacturer. a parallel resona nt, fundamen- tal frequency, microprocessor gr ade crystal should be used for this configuration. if a buffered, shaped clock is used, this external clock connects to the dsp?s clkin pin. clkin input cannot be halted, changed, or operated below the specified frequency during normal operation. this clock signal should be a ttl compatible signal. when an external clock is used, the xtal input mu st be left unconnected. the dsp provides a user programmable 1 to 32 multi- plication of the input clock, including some fractional values, to support 128 external to internal (dsp core) clock ratios. the bypass pin, and msel6?0 and df bits, in the pll configuration register, d ecide the pll multiplication factor at reset. at runtime, th e multiplication factor can be controlled in software. to support input clocks greater that 100 mhz, the pll uses an additional bit (df). if the input clock is g reater than 100 mhz, df must be set. if the input clock is less than 100 mhz, df must be cleared. for clock multiplier settings, see the adsp-21992 dsp hardware reference manual . the peripheral clock is supplied to the clkout pin. all on chip peripherals for the adsp-21992 operate at the rate set by the peripheral clock. the peripheral clock (hclk) is either equa l to the core clock rate or one half the dsp core clock rate (cclk). th is selection is controlled by the iosel bit in the p llctl register. the maximum core clock is 160 mhz, and th e maximum peripheral clock is 80 mhz?the combination of the input clock and core/peripheral clock ratios may not exceed these limits. reset and power on reset (por) the reset pin initiates a complete hardware reset of the adsp-21992 when pulled low. the reset signal must be asserted when the device is po wered up to assure proper initialization. the adsp-21992 contains an integrated power on reset (por) circuit that provides an output reset signal, por , from the adsp-21992 on power up and if the power supply voltage falls below the threshold level. the adsp-21992 may be reset from an external source using the reset signal or alternatively the internal power on reset circuit may be used by connecting the por pin to the reset pin. during power up the reset line must be activated for long enough to allow the dsp core's internal clock to stabilize. the power up sequence is defined as the total time required for the crystal oscillator to stabilize after a valid vdd is applied to the processor and for the internal phase locked loop (p ll) to lock onto the specific crystal frequency. a minimum of 2000 cy cles will ensure that the pll has locked (this does not include the crys tal oscillator start up time). the reset input contains some hyst eresis. if using an rc circuit to generate your reset signal, the circuit should use an external schmidt trigger. the master reset sets all internal stack pointers to the empty stack condition, masks all interrupts, and resets all registers to their default values (where applicable). when reset is released, if there is no pendin g bus request, program control jumps to the location of the on chip boot rom (0xff0000) and the booting sequence is performed. power supplies the adsp-21992 has separate power supply connections for the internal (v ddint ) and external (v ddext ) power supplies. the internal supply must meet the 2.5 v require- ment. the external supply mu st be connected to a 3.3 v supply. all external supply pi ns must be connected to the same supply. figure 5. external crystal connections clkin xtal adsp-2199x 50mhz
for current information contact analog devices at (781) 937-1799 adsp-21992 august 2002 this information applies to a product under development. its characteristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 14 rev. pra preliminary technical data booting modes the adsp-21992 supports a number of different boot modes that are controlled by the three dedicated hardware boot mode control pins (bmode2, bmode1 and bmode0). the use of 3 boot mode control pins means that up to 8 different boot modes are possible. of these only 5 modes are valid on the adsp-21992. the adsp-21992 exposes the boot mechanism to software control by providing a nonmaskable boot interrupt that vectors to the start of the on chip rom memory block (at address 0xff0000). a boot interrupt is automatically initiated following either a hardware initiated reset, via the reset pin, or a software initiated reset, via writing to the software reset register following either a hardware or a software reset, execution always starts from the boot rom at address 0xff0000, irrespective of the settings of the bmode2, bmode1 and bmode0 pins. the dedicated bmode2, bmode1 and bmode0 pins are sampled during hardware reset. the particular boot mode fo r the adsp-21992 associated with the settings of the bmode2, bmode1, bmode0 pins is defined in table 1. instruction set description the adsp-21992 assembly langua ge instruction set has an algebraic syntax that was desi gned for ease of coding and readability. the assembly language, which takes full advantage of the processor?s un ique architecture, offers the following benefits: ? adsp-219x assembly language sy ntax is a superset of and source code compatible (excep t for two data registers and dag base address registers) with adsp-21xx family syntax. it may be necessary to restructure adsp-21xx programs to accommodate the adsp-21992?s unified memory space and to conform to its interrupt vector map. ? the algebraic syntax eliminates the need to remember cryptic assembler mnemonics. for example, a typical arithmetic add instruction, such as ar = ax0 + ay0, resembles a simple equation. ? every instruction, but two, assembles into a single, 24-bit word that can execute in a si ngle instruction cycle. the exceptions are two dual word instructions. one writes 16- or 24-bit immediate data to memory, and the other is an absolute jump/call with the 24- bit address specified in the instruction. ? multifunction instructions allow parallel execution of an arithmetic, mac, or shift instruction with up to two fetches or one write to processor memory space during a single instruction cycle. ? program flow instructions support a wider variety of con- ditional and unconditional jumps/calls and a larger set of conditions on which to base execution of conditional instructions. development tools the adsp-21992 is supported with a complete set of software and hardware development tools, including analog devices? emulators and visual dsp? development environ- ment. the same emulator hardware that supports other adsp-219x dsps, also fully emulates the adsp-21992. the visualdsp project management environment lets pro- grammers develop and debug an application. this environment includes an easy-to-use assemb ler that is based on an algebraic syntax; an archiver (librarian/library builder); a linker; a loader; a cycle-accurate, instruc- tion-level simulator; a c/ c++ compiler; and a c/c++ run-time library that includes dsp and mathematical func- tions. two key points for these tools are: ? compiled adsp-219x c/c++ code efficiency?the compiler has been developed for efficient translation of c/c++ code to adsp-219x assembly. the dsp has architectural features that improve the efficiency of compiled c/c++ code. ? adsp-218x family code compatibility?the assembler has legacy features to ease the conversion of existing adsp-218x applications to the adsp-219x. debugging both c/c++ and assembly programs with the visualdsp debugger, programmers can: ? view mixed c/c++ and asse mbly code (interleaved source and object information) ? insert break points ? set conditional breakpoints on registers, memory, and stacks table 3. summary of boot modes for adsp-21992 boot mode bmode2 bmode1 bmode0 function 0 0 0 0 illegal ? reserved 1 0 0 1 boot from external 8-bit memory over emi 2 0 1 0 execute from external 8-bit memory 3 0 1 1 execute from external 16-bit memory 4100boot from spi0 4 kbits 5101boot from spi0 > 4kbits 6 1 1 0 illegal ? reserved 7 1 1 1 illegal ? reserved
this information applies to a product under development. its charac teristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 15 rev. pra for current information contact analog devices at (781) 937-1799 adsp-21992 august 2002 preliminary technical data ? trace instruction execution ? profile program execution ? fill and dump memory ? source level debugging ? create custom debugger windows the visualdsp ide lets programmers define and manage dsp software development. its dialog boxes and property pages let programmers configure and manage all of the adsp-219x development tools, including the syntax high- lighting in the visualdsp edit or. this capability permits: ? control how the development tools process inputs and generate outputs. ? maintain a one-to-one corr espondence with the tool?s command line switches. analog devices dsp emulators use the ieee 1149.1 jtag test access port of the adsp -21992 processor to monitor and control the target board processor during emulation. the emulator provides full-s peed emulation, allowing inspection and modifi cation of memory, registers, and processor stacks. nonintrusive in-circuit emulation is assured by the use of the pr ocessor?s jtag interface?the emulator does not affect targ et system loading or timing. in addition to the software and hardware development tools available from analog devices, third parties provide a wide range of tools supporting th e adsp-219x processor family. hardware tools include adsp -219x pc plug-in cards. third party software tools include dsp libraries, real-time operating systems, and block diagram design tools. designing an emulator compatible dsp board (target) the white mountain dsp (p roduct line of analog devices, inc.) family of emulators are tools that every dsp developer needs to test an d debug their hardware and software system. analog de vices has supplied an ieee 1149.1 jtag test access port (tap) on each jtag dsp. the emulator uses the tap to access the internals of the dsp, allowing the developer to load code, set breakpoints, observe variables, observe memory, examine registers, etc. the dsp must be halted to send data and commands, but once an operation is complete d by the emulator, the dsp system is set running at full sp eed with no impa ct on system timing. to use these emulators, the targ et?s design must include the interface between an analog devices jtag dsp and the emulation header on a cust om dsp target board. the following sections provide the gu idelines for design that help eliminate possible jtag emulation port problems. target board connector the emulator interface to an adi jtag dsp is a 14-pin header, as shown in figure 6 . the customer must supply this header on thei r target board in order to communicate with the emulator. the interfa ce consists of a standard dual row 0.025" square post header, set on 0.1" x 0.1" spacing, with a minimum post length of 0.235". pin 3 is the key position used to prevent the pod from being inserted back- wards. this pin must be clipped on the target board. also, the clearance (length, width, and height) around the header must be considered. leave a clearance of at least 0.15? and 0.10? around the leng th and width of the header, and reserve a height clearance to attach and detach the pod connector. for more information, see layout require- ments on page 17 . as can be seen in figure 6 , there are two sets of signals on the header. there are the standard jtag signals tms, tck, tdi, tdo, trst and , emu used for emulation p u r p o s e s ( v i a a n e m u l a t o r ) . there are also secondary jtag signals btms, btck, btdi, and btrst that are option- ally used for board-level (boundary scan) testing. the "b" signals would be connected to a separate on-board jtag boundary scan controller if us ed. most customers will never use the "b" signals. if they w ill not be used, tie all of them to ground as shown in figure 2. note: btck can alternately be pulled up (for some older silicon) to vdd (+5v, +3.3v, or +2.5v) using a 4.7k resistor, as described in previous documents. tying the signal to ground is universal and will work for all silicon. when the emulator is not conn ected to this header, place jumpers across btms, btck, btrst , and btdi as shown in figure 7 . this holds the jtag signals in the correct state to allow the dsp to run free. remove all the jumpers when connecting the emulator to the jtag header. figure 6. jtag ta rget board connector for jtag equiped analog devices dsp (jumpers in place) top view 13 14 11 12 910 9 78 56 34 12 emu gnd tms tck trst tdi tdo gnd key (no pin) btms btck btrst btdi gnd
for current information contact analog devices at (781) 937-1799 adsp-21992 august 2002 this information applies to a product under development. its characteristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 16 rev. pra preliminary technical data the state of each standard jt ag signal can be found in table 4 . the dsp clkin signal is the clock signal line (typically 30 mhz or greater) that connects an oscillator to all dsps in multiple dsp systems requiring synchronization. for syn- chronous dsp operations to work correctly the clkin signal on all the dsps must be the same signal and the skew between them must be minimal (use clock drivers, or other means) ? see the dsp users guide for more details on clkin. note that the clkin signal is not used by the emulator and can cause noise problems if co nnected to the jtag header. legacy documents show it conn ected to pin 4 of the jtag header. pin-4 should be tied to ground on the 14-pin jtag header (do not connect the jtag header pin to the dsp clkin signal). if you have already connected it to the jtag header pin, and are ex periencing noise from this signal, simply clip this pin on the 14-pin jtag header. the final connections between a single dsp target and the emulation header (within 6 inches) are shown in figure 8 . a 4.7k pull-up resistor has been added on tck, tdi and tms chain for incr eased noise resistance. should your design use more than one dsp (or other jtag device in the scan chain), or if your jtag header is more than 6 inches from the ds p, use a buffered connection scheme as shown in figure 9 (no local boundary scan mode shown). to keep signal skew to a minimum, be sure the buffers are all in the same physical package (typical chips have 6, 8, or 16 drivers). using a buffer that has built in series resistors such as th e 74abt2244 family can help reduce ringing on the jtag signal lines. for low voltage applications (3.3v, 2.5v, and 1.8v i/o), the 74alvt, and 74avc logic families are a good starting point. also, note the position of the pull-up resistor on emu . this is required since the emu line is an open drain signal. important: if you have more than one dsp (or jtag device) on your target (in the scan chain), it is imperative that you buffer the jtag header. this will k eep the signals clean and avoid noise problems th at occur with longer signal traces (ultimately resulting in reliable emulator operation). although the theoretical numb er of devices that can be supported (by the software) in one jtag scan chain is quite large (50 devices or more) it is not recommended that you use more than eight physical devices in one scan chain. (a physical device could however contain many jtag devices such as inside a multi-chip module). the recommendation of not more than eight physical devices is mostly due to the transmission line effects that ap pear in long signal traces, and based on some field-collect ed empirical data. the best approach for large numbers of physical devices is to break the chain into several smaller independent chains, each with their own jtag header and buffer. if this is not possible, at least add some jumpers th at can reduce the number of devices in one chain for debu g purposes, and pay special attention in the layout stage for transmission line effects. figure 7. jtag target boar d connector with no local boundary scan table 4. state of standard jtag signals 1 1 o = output, i = input, o/d = open drain signal description emulator dsp tms test mode select o i tck test clock (10 mhz) o i trst test reset o i tdi test data in o i tdo test data out i o emu emulation pin i o, o/d top view 13 14 11 12 910 9 78 56 34 12 emu gnd tms tck trst tdi tdo gnd key (no pin) btms btck btrst btdi gnd figure 8. single-dsp jtag-connections, unbuffered top view 13 14 11 12 910 9 78 56 34 12 emu gnd tms tck trst tdi tdo gnd key (no pin) btms btck btrst btdi gnd 4 . 7 k 4 . 7 k 4 . 7 k vdd emu tms tck trst tdi tdo 6 inches or less jtag connector dsp jtag port
this information applies to a product under development. its charac teristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 17 rev. pra for current information contact analog devices at (781) 937-1799 adsp-21992 august 2002 preliminary technical data layout requirements all jtag signals (tck, tms, tdi, tdo, emu , and trst ) should be treated as crit ical route signals. this means pay special attention wh en routing these signals. specify a controlled impedan ce requirement for each route (value depends on your circuit board - typically 50-75 ). keep crosstalk and inductance to a minimum on these lines by using a good ground plane and by routing away from other high noise signals such as clock lines. keep these routes as short and clean as possible, and keep the bused signals (tms, tck, trst and, emu ) as close to the same length as possible. note: the jtag tap relies on the state of the tms line and the tck clock signal. if th ese signals have glitches (due to ground bounce, crosstalk, etc.) unreliable emulator operation will result. if you are experiencing emulator problems, look at these signal s using a high-speed digital oscilloscope. these lines must be clean, and may require special termination schemes. if you are buffering the jtag header (most customers will) you must provide signal ter- mination appropriate for your ta rget board (series, parallel, r/c, etc.). power sequence the power-on sequence for yo ur target and emulation system is as follows: apply po wer to the emulator first, then to the target board. this en sures that the jtag signals are in the correct state for the dsp to run free. upon power-on, the emulator drives the trst signal low, keeping the dsp tap in the test-logic-reset state, until the emulation software takes control. removal of power should be the reverse: turn off power to th e target board then to the emulator. emulator model specifics the following sections contain design details on various emulator pod designs by white mountain dsp. the emulator pod is the device that connects directly to the dsp target board 14-pin jtag header. check our web site for updates to this document that will contain new emulator design details. white mountain dsp jtag pod connector this section applies to the mountain ice, summit-ice, trek-ice, mountain-ice/ws, apex-ice. figure 10 details the dimensions of the jtag pod connector at the 14-pin target end. figure 11 displays the keep-out area for a target board header. the keep-out area allows the pod connector to properly seat onto the target board header. this board area should contain no components (chips, resistors, capacitors, etc.). the dimensions are referenced to the center of the 0.25? square post pin. white mountain dsp 3.3v pod logic this section applies to mountain ice, summit-ice, trek-ice, mountain-ice/ws, apex-ice. a portion of the white mountain dsp 3.3v emulator pod interface is shown in figure 12 . this figure describes the driver circuitry of the emulator pod. as can be seen, tms, tck and tdi are driven with a 33 series resistor. trst is driven with a 100 series resistor. tdo and clkin are figure 9. multiple-dsp jtag-connections, buffered emu trst e m u t r s t e m u t m s t c k t r s t tdi tdo e m u t r s t top view 13 14 11 12 910 9 78 56 34 12 gnd tms tck tdi tdo gnd key (no pin) btms btck btrst btdi gnd 4 . 7 k 4 . 7 k 4 . 7 k vdd jtag connector dsp p0 4 . 7 k 4 . 7 k t m s t c k tdi tdo dsp p1 dsp p# buffers t m s t c k tdi tdo
for current information contact analog devices at (781) 937-1799 adsp-21992 august 2002 this information applies to a product under development. its characteristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 18 rev. pra preliminary technical data terminated with an optional 91/120 parallel terminator. emu is pulled up with a 4.7k resistor. the 74lvt244 chip drives the signals at 3.3v, with a maximum current rating of 32ma. you can parallel terminate the tms, tck, trst , and tdi lines locally on your target bo ard, if needed, since they are driven by the pod with sufficien t current drive (32ma). in order to use the terminators on the tdo line (clkin is not used), you must have a buffer on your target board jtag header. the dsp is not capable of driving the parallel terminator load directly with tdo. assuming you have the proper buffers, you may use th e optional parallel termina- tors simply by placing a jumper on j2. white mountain dsp 2.5v pod logic this section applies to mountain ice, summit-ice, trek-ice, mountain-ice/ws. a portion of the white mountain dsp 2.5v emulator pod interface is shown in figure 13 . this figure describes the driver circuitry of the emulator pod. as can be seen, tms, tck, and tdi are driven with a 33 series resistor. trst is driven with a 100 series resistor. tdo is pulled up with a 4.7k resistor and terminated with an optional parallel terminator that can be configured by the user. emu is pulled up with a 4.7k resistor. the clkin signal is not used and not connected inside the pod. the 74alvt16244 chip drives the signals at 2.5v, with a maximum current rating of 8ma. you can terminate the tms, tck, trst , and tdi lines locally on your target board, if needed, as long as the termi- nator?s current use does not exceed the driver?s maximum current supply (8ma). in or der to use the terminator on the tdo line, you must have a buffer on your target board jtag header. the dsp is not capable of driving a parallel terminator load (typically 50-75 ) directly with tdo. assuming you have the proper buffers, you may use the optional parallel terminator by adding the appropriate resistors and placing a jumper on j2. additional information this data sheet provides a general overview of the adsp-21992 architecture and fu nctionality. for detailed information on the adsp-21992 embedded dsp core figure 10. jtag pod connector dimensions figure 11. jtag pod connector keep-out area figure 12. 3.3v jtag pod driver logic figure 13. 2.5v jtag pod driver logic
this information applies to a product under development. its charac teristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 19 rev. pra for current information contact analog devices at (781) 937-1799 adsp-21992 august 2002 preliminary technical data architecture, instru ction set, communications ports and embedded control peripherals, refer to the adsp-21992 mixed signal dsp controller hardware reference manual . pin descriptions adsp-21992 pin definitions are listed in table 5 . all adsp-21992 inputs ar e asynchronous and can be asserted asynchronously to clki n (or to tck for trst ). unused inputs should be tied or pulled to v ddext or gnd, except for addr21?0, data15?0 , pf7-0, and inputs that have internal pullup or pulldown resistors (trst , bmode0, bmode1, bmode2 , bypass, tck, tms, tdi, pwmpol, pwmsr , and reset )?these pins can be left floating. these pins have a logic level hold circuit that prevents input from floating internally. pwmtrip has an internal pulldown, but should not be left floating to avoid unnecessary pwm shutdowns. the following symbols appear in the type column of table 5 : g = ground, i = input, o = output, p = power supply, b = bidirectional, t = three state, d = digital, a = analog, ckg = clock generation pin, pu = internal pull up, pd = internal pull down, and od = open drain. table 5. adsp-21992 pin descriptions signal name type description a19 - a0 d, ot external port address bus d15 - d0 d, bt external port data bus rd d, ot external port read strobe wr d, ot external port write strobe ack d, i external port access ready acknowledge br d, i, pu external port bus request bg d, o external port bus grant bgh d, o external port bus grant hang ms0 d, ot external port memory select strobe 0 ms1 d, ot external port memory select strobe 1 ms2 d, ot external port memory select strobe 2 ms3 d, ot external port memory select strobe 3 ioms d, ot external port io space select strobe bms d, ot external port boot memory select strobe clkin d,i,ckg clock input/oscillator input/ crystal connection 0 xtal d,o,ckg oscillator output/ crystal connection 1 clkout d, ot clock output (hclk) bypass d, i, pu pll bypass mode select reset d, i, pu processor reset input por d, o power on reset output bmode2 d, i, pu boot mode select input 2 bmode1 d, i, pd boot mode select input 1 bmode0 d, i, pu boot mode select input 0 tck d, i jtag test clock tms d, i, pu jtag test mode select tdi d, i, pu jtag test data input tdo d, ot jtag test data output trst d, i, pu jtag test reset input emu d, ot, pu emulation status vin0 a, i adc input 0 vin1 a, i adc input 1 vin2 a, i adc input 2 vin3 a, i adc input 3 vin4 a, i adc input 4 vin5 a, i adc input 5 vin6 a, i adc input 6 vin7 a, i adc input 7 ashan a, i inverting sha_a input bshan a, i inverting sha_b input
this information applies to a product under development. its charac teristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 20 rev. pra for current information contact analog devices at (781) 937-1799 adsp-21992 august 2002 preliminary technical data capt a, o noise reduction pin capb a, o noise reduction pin vref a, i, o voltage reference pin (mode selected by state of sense) sense a, i voltage re ference select pin cml a, o common mode level pin convst d, i adc convert start input canrx d, i controller area network (can) receive cantx d, o, od controller area network (can) transmit pf15 d, bt, pd general purpose io15 pf14 d, bt, pd general purpose io14 pf13 d, bt, pd general purpose io13 pf12 d, bt, pd general purpose io12 pf11 d, bt, pd general purpose io11 pf10 d, bt, pd general purpose io10 pf9 d, bt, pd general purpose io9 pf8 d, bt, pd general purpose io8 pf7/spisel7 d, bt, pd general purpose io7 / spi slave select output 7 pf6/spisel6 d, bt, pd general purpose io6 / spi slave select output 6 pf5/spisel5 d, bt, pd general purpose io5 / spi slave select output 5 pf4/spisel4 d, bt, pd general purpose io4 / spi slave select output 4 pf3/spisel3 d, bt, pd general purpose io3 / spi slave select output 3 pf2/spisel2 d, bt, pd general purpose io2 / spi slave select output 2 pf1/spisel1 d, bt, pd general purpose io1 / spi slave select output 1 pf0/spiss0 d, bt, pd general purpose io0 / spi slave select input 0 sck d, bt spi clock miso d, bt spi master in slave out data mosi d, bt spi master out slave in data dt d, ot sport data transmit dr d, i sport data receive rfs d, bt sport receive frame sync tfs d, bt sport transmit frame sync tclk d, bt sport transmit clock rclk d, bt sport receive clock eia d, i encoder a channel input eib d, i encoder b channel input eiz d, i encoder z channel input eis d, i encoder s channel input aux0 d, o auxiliary pwm channel 0 output aux1 d, o auxiliary pwm channel 1 output auxtrip d, i, pd auxiliary pwm shutdown pin tmr2 d, bt timer 0 input/output pin tmr1 d, bt timer 1 input/output pin tmr0 d, bt timer 2 input/output pin ah d, o pwm channel a hi pwm al d, o pwm channel a lo pwm bh d, o pwm channel b hi pwm bl d, o pwm channel b lo pwm ch d, o pwm channel c hi pwm cl d, o pwm channel c lo pwm pwmsync d, bt pwm synchronization pwmpol d, i, pu pwm polarity pwmtrip d, i, pd pwm trip table 5. adsp-21992 pin descriptions (continued) signal name type description
this information applies to a product under development. its charac teristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 21 rev. pra for current information contact analog devices at (781) 937-1799 adsp-21992 august 2002 preliminary technical data pwmsr d, i, pu pwm sr mode select avdd (2 pins) a, p analog supply voltage avss (2 pins) a, g analog ground vddint (6 pins) d, p digital internal supply vddext (10 pins) d, p digital external supply gnd (16 pins) d, g digital ground table 5. adsp-21992 pin descriptions (continued) signal name type description
this information applies to a product under development. its charac teristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 22 rev. pra for current information contact analog devices at (781) 937-1799 adsp-21992 august 2002 preliminary technical data adsp-21992?specifications recommended operating conditions parameter description 1 min max unit v ddint internal (core) supply voltage 2.37 2.63 v v ddext external (i/o) supply voltage tbd 3.6 v v ih1 high level input voltage 2 , @ v ddint = max 2.0 v ddext v v ih2 high level input voltage 3 , @ v ddint = max 2.2 v ddext v v il low level input voltage 1, 2 , @ v ddint = min ?0.3 0.6 v t amb ambient operating temperature ?40oc +85oc oc 1 specifications subject to change without notice. 2 applies to input and bidirectional pins: data15?0 , had15?0, ha16, hale, ha ck, hack_p, bypass, hrd , hwr , ack, pf7?0, hcms , hcioms , br , tfs, tfs1, tfs2/mosi0, rfs, rfs1 , rfs2/mosi1, bmode2, bmode1?0, tms, tdi, tck, dt2/miso0, dr, dr1, dr2/miso1, tclk, tclk1, tclk2/ sck0, rclk, rclk1, rclk2/sck1. 3 applies to input pins: clkin, reset , trst . electrical characteristics parameter 1 description test conditions min max unit v oh high level output voltage 2 @ v ddext = min, i oh = ?0.5 ma 2.4 v v ol low level output voltage 2 @ v ddext = min, i ol = 2.0 ma 0.4 v i ih high level input current 3, 4 @ v ddext = max, v in = v dd max tbd a i il low level input current 2 @ v ddint = max, v in = 0 v tbd a i ilp low level input current 3 @ v ddint = max, v in = 0 v tbd a i ozh three state leakage current 5 @ v ddint = max, v in = v dd max tbd a i ozl three state leakage current 4 @ v ddint = max, v in = 0 v tbd a i ozhp three state leakage current 6 @ v ddint = max, v in = v dd max tbd a i ozls three state leakage current 5 @ v ddint = max, v in = 0 v tbd a i idd typical supply current (internal) @ t ck = tbd ns, v ddint = max tbd ma i idd idle supply current (internal) @ t ck = tbd ns, v ddint = max tbd ma i idd pwrdwn supply current (internal) @ t ck = tbd ns, v ddint = max tbd ma c in input capacitance 7, 8 f in = 1 mhz, t case = 25c, v in = 2.5 v tbd pf 1 specifications subject to change without notice.
this information applies to a product under development. its charac teristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 23 rev. pra for current information contact analog devices at (781) 937-1799 adsp-21992 august 2002 preliminary technical data absolute maximum ratings esd sensitivity timing specifications this section contai ns timing information for the dsp?s external signals. 2 applies to output and bidirectional pi ns: data15?0, addr21 ?0, had15?0, ms3?0 , ioms , rd , wr , clkout, hack, pf7?0, tmr2?0, bgh , bg , dt, dt1, dt2/miso0, tclk, tclk1, tclk 2/sck0, rclk, rclk1, rclk2/sck1, tfs, tfs 1, tfs2/mosi0, rfs, rfs1, rfs2/mosi1, bms , tdo, txd, emu . 3 applies to input pins: ack, br , hcms , hcioms , bmode2, bmode1?0 , ha16, hale, hrd , hwr , clkin, reset , tck, tdi, tms, trst , dr, dr1, bypass, rxd. 4 applies to input pins with internal pull ups: trst , bmode0, bmode1, bmode2, bypass, tck, tms, tdi, reset . 5 applies to three statable pi ns: data15?0, addr21?0, ms3?0 , rd , wr , pf7?0, bms , ioms , tfsx, rfsx, tdo, emu . 6 the test program used to measure i ddinpeak represents worst case processor operation and is not sustainable under normal application conditions. actual internal power measurements made using typical applications are less than specified. for more information, see power dissipation on page 42. 7 applies to all signal pins. 8 guaranteed, but not tested. v ddint internal (core) supply voltage 1,2 . . . . . . ?0.3 to 3.0 v v ddext external (i/o) supply voltage . . . . . . . . ?0.3 to 4.6 v v il ?v ih input voltage . . . . . . . . . . . . . . . . . . ?0.5 to +5.5 v 3 v ol ?v oh output voltage swing . . . . . . . . . . . ?0.5 to +5.5 v 3 c l load capacitance . . . . . . . . . . . . . . . . . . . . . . . . 200 pf t cclk core clock period . . . . . . . . . . . . . . . . . . . . . . 6.25 ns f cclk core clock frequency . . . . . . . . . . . . . . . . . 160 mhz t hclk peripheral clock period . . . . . . . . . . . . . . . . . . . . 10 ns f hclk peripheral clock frequency . . . . . . . . . . . . . . 80 mhz t store storage temperature range . . . . . . . . . .?65 to 150oc t lead lead temperature (5 seconds) . . . . . . . . . . . . . 185oc 1 specifications subject to change without notice. 2 stresses greater than those listed above may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 3 except clkin and analog pins. caution: esd (electrostatic discharge) sensitive de vice. electrostatic ch arges as high as 4000v readily accumulate on the human body and test equipment and ca n discharge without detection. although the adsp-21992 featur es proprietary esd protection circuitry, permanent damage may occur on devices su bjected to high-ene rgy electrostatic discharges. therefore, proper esd precaut ions are recommended to avoid perfor- mance degradation or loss of functionality.
preliminary technical data this information applies to a product under development. its charac teristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 24 rev. pra for current information contact analog devices at (781) 937-1799 adsp-21992 august 2002 clock in and clock out cycle timing table 6 and figure 14 describe clock and reset operations. per v ddint internal (core) supply voltage, ?0.3 to 3.0 v on page 23 , combinations of clkin and clock mu ltipliers must not select core/peripheral clocks in excess of 160/100 mhz. table 6. clock in and clock out cycle timing parameter description min max unit switching characteristic t ckod clkout delay from clkin 0 5.8 ns t cko clkout period 1 1 figure 14 shows a 2 ratio between clkout = 2 clkin (or t hclk = 2 t cclk ), but the ratio has many programmable options. for more information see the system design chapter of the adsp-219x/2191 dsp hardware reference . 10 ns timing requirements t ck clkin period 2,3 2 in clock multiplier mode and msel6?0 set for 1:1 (or clkin=cclk), t ck =t cclk . 3 in bypass mode, t ck =t cclk . 6.25 200 ns t ckl clkin low pulse 2.2 ns t ckh clkin high pulse 2.2 ns t wrst reset asserted pulsewidth low 200t clkout ns t msls mselx/bypass stable before reset de-asserted setup 450 s t mslh mselx/bypass stable after reset de-asserted hold 10t clkout ns figure 14. clock in and clock out cycle timing t ckod clkout msel6?0 bypass reset clkin t wrst t ckh t ck t ckl t mslh t msls t cko
preliminary technical data this information applies to a product under development. its charac teristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 25 rev. pra for current information contact analog devices at (781) 937-1799 adsp-21992 august 2002 programmable flags cycle timing table 7 and figure 15 describe programmable flag operations. table 7. programmable flags cycle timing parameter description min max unit switching characteristic t dfo flag output delay with respect to hclk 3 ns t hfo flag output hold after hclk high tbd tbd ns timing requirement t hfi flag input hold is asynchronous 3 ns figure 15. programmable flags cycle timing flag input pf (input) pf (output) hclk t hfi flag output t dfo t dfo t hfo
preliminary technical data this information applies to a product under development. its charac teristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 26 rev. pra for current information contact analog devices at (781) 937-1799 adsp-21992 august 2002 timer pwm_out cycle timing table 8 and figure 16 describe timer expired operations. the input sign al is asynchronous in ?width capture mode? and has an absolute maximum input frequency of 50 mhz. table 8. timer pwm_out cycle timing parameter description min max unit switching characteristic t hto timer pulsewidth output 1 1 the minimum time for t hto is one cycle, and the maximum time for t hto equals (2 32 ?1) cycles. 6.25 (2 32 ?1) cycles ns figure 16. timer pwm_out cycle timing hclk pwm_out t hto
preliminary technical data this information applies to a product under development. its charac teristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 27 rev. pra for current information contact analog devices at (781) 937-1799 adsp-21992 august 2002 external port write cycle timing table 9 and figure 17 describe external port write operations. the external port lets systems extend re ad/write accesses in three ways: wait stat es, ack input, and co mbined wait states and ack. to add waits with ack, the dsp must see ack low at the rising edge of emi clock. ack low causes the dsp to wait, and the dsp requires two emi cloc k cycles after ack goes hi gh to finish the access. for more information, see the external port chapter in the adsp-219x/2191 dsp hardware reference table 9. external port write cycle timing parameter description 1, 2, 3 1 t hclk is the peripheral clock period. 2 these are preliminary timing parameters that are based on worst case operating conditions. 3 the pad loads for these timing parameters are 20 pf. min max unit switching characteristics t cwa emi 4 clock low to wr asserted delay 4 emi clock is the external port clock that is generated from the em i clock ratio. this signal is not available on an external pi n, but (roughly) corresponds to hclk (at similar clock ratios). 2.8 ns t csws chip select asserted to wr de-asserted delay 4.3 6.5 ns t aws address valid to wr setup and delay 4.9 7.0 ns t aks ack asserted to emi clock high delay 6.0 ns t wscs wr de-asserted to chip se lect de-asserted 4.8 7.0 ns t wsa wr de-asserted to address invalid 4.5 6.6 ns t cwd emi clock low to wr de-asserted delay 2.5 2.7 ns t ww wr strobe pulsewidth t hclk ?0.5 ns t cda wr to data enable access delay 1.5 4.1 ns t cdd wr to data disable access delay 3.3 7.4 ns t dsw data valid to wr de-asserted setup t hclk ?1.4 t hclk +4.8 ns t dhw wr de-asserted to data invalid hold time; wt_hold=0 3.4 7.4 ns t dhw wr de-asserted to data invalid hold time; wt_hold=1 t hclk +3.4 t hclk +7.4 ns timing requirement t akw ack strobe pulsewidth 10.0 ns
preliminary technical data this information applies to a product under development. its charac teristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 28 rev. pra for current information contact analog devices at (781) 937-1799 adsp-21992 august 2002 figure 17. external port write cycle timing d15?0 ack wr a21?0 ms3?0 ioms bms emi clock t cwa t aws t cwd t ww t ak w t dsw t dhw t csws t wsa t wscs t cd a t aks
preliminary technical data this information applies to a product under development. its charac teristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 29 rev. pra for current information contact analog devices at (781) 937-1799 adsp-21992 august 2002 external port read cycle timing table 10 and figure 18 describe external port read operations. for ad ditional information on the ack signal, see the discussion on on page 27 . table 10. external port read cycle timing parameter description 1, 2, 3 1 t hclk is the peripheral clock period. 2 these are preliminary timing parameters that are based on worst case operating conditions. 3 the pad loads for these timing parameters are 20 pf. min max unit switching characteristics t cra emi 4 clock low to rd asserted delay 4 emi clock is the external port clock that is generated from the em i clock ratio. this signal is not available on an external pi n, but (roughly) corresponds to hclk (at similar clock ratios). 2.8 ns t csrs chip select asserted to rd asserted delay 4.3 6.5 ns t ars address valid to rd setup and delay 4.9 7.0 ns t aks ack asserted to emi clock high delay 6.0 ns t crd emi clock low to rd de-asserted delay 2.5 2.7 ns t rscs rd de-asserted to chip select de-asserted setup 4.8 7.0 ns t rw rd strobe pulsewidth t hclk ?0.5 ns t rsa rd de-asserted to address invalid setup 4.5 6.6 ns timing requirements t akw ack strobe pulsewidth 10.0 ns t cda rd to data enable access delay 0.0 ns t rda rd asserted to data access setup t hclk ?5.5 ns t ada address valid to data access setup t hclk ?0.2 ns t sda chip select asserted to data access setup t hclk ?0.6 ns t sd data valid to rd de-asserted setup 1.8 ns t hrd rd de-asserted to data invalid hold 0.0 ns
preliminary technical data this information applies to a product under development. its charac teristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 30 rev. pra for current information contact analog devices at (781) 937-1799 adsp-21992 august 2002 figure 18. external port read cycle timing d15?0 ack rd a21?0 ms3?0 ioms bms emi clock t cra t ars t crd t rw t akw t cda t rda t ada t sda t sd t hrd t csrs t rsa t rscs t aks
preliminary technical data this information applies to a product under development. its charac teristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 31 rev. pra for current information contact analog devices at (781) 937-1799 adsp-21992 august 2002 external port bus request and grant cycle timing table 11 and figure 19 describe external port bus request and bus grant operations. table 11. external port bus request and grant cycle timing parameter description 1, 2, 3 1 t hclk is the peripheral clock period. 2 these are preliminary timing parameters that are based on worst case operating conditions. 3 the pad loads for these timing parameters are 20 pf. min max unit switching characteristics t sd clkout high to xms , address, and rd /wr disable 4.3 ns t se clkout low to xms , address, and rd /wr enable 4.0 ns t dbg clkout high to bg asserted setup 2.2 ns t ebg clkout high to bg de-asserted hold time 2.2 ns t dbh clkout high to bgh asserted setup 2.4 ns t ebh clkout high to bgh de-asserted hold time 2.4 ns timing requirements t bs br asserted to clkout high setup 4.6 ns t bh clkout high to br de-asserted hold time 0.0 ns
preliminary technical data this information applies to a product under development. its charac teristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 32 rev. pra for current information contact analog devices at (781) 937-1799 adsp-21992 august 2002 figure 19. external port bus request and grant cycle timing t bh br a21?0 ms3?0 ioms bms clkout bg wr rd bgh t bs t sd t sd t sd t dbg t dbh t se t se t se t ebg t ebh
preliminary technical data this information applies to a product under development. its charac teristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 33 rev. pra for current information contact analog devices at (781) 937-1799 adsp-21992 august 2002 serial port (sport) clocks and data timing table 12 and figure 20 describe sport transmit and receive operations. table 12. serial port (sport) clocks and data timing 1 1 to determine whether communication is possible between two devices at clock speed n, the following specifications must be confi rmed: 1) frame sync delay and frame sync setup and hold, 2) da ta delay and data setup and hold, and 3) sclk width. parameter description min max unit switching characteristics t hofse rfs hold after rclk (internally generated rfs) 2 2 referenced to drive edge. 0 12.4 ns t dfse rfs delay after rclk (internally generated rfs) 2 0 12.4 ns t ddten transmit data delay after tclk 2 0 12.1 ns t ddtte data disable from external tclk 2 0 12.0 ns t ddtin data enable from internal tclk 2 06.8ns t ddtti data disable from internal tclk 2 06.3ns timing requirements t sclkiw tclk/rclk width 20 ns t sfsi tfs/rfs setup before tclk/rclk 3 3 referenced to sample edge. ?0.6 ns t hfsi tfs/rfs hold after tclk/rclk 3, 4 4 rfs hold after rclk when mce = 1, mfd = 0 is 0 ns minimum from dr ive edge. tfs hold after tclk for late external tfs is 0 ns mini mum from drive edge. ?0.3 ns t sdri receive data setup before rclk 3 ?2.3 ns t hdri receive data hold after rclk 3 1.9 ns t sclkw tclk/rclk width 20 ns t sfse tfs/rfs setup before tclk/rclk 3 ?0.6 ns t hfse tfs/rfs hold after tclk/rclk 3, 4 ?0.6 ns t sdre receive data setup before rclk 3 ?2.2 ns t hdre receive data hold after rclk 3 1.8 ns
preliminary technical data this information applies to a product under development. its charac teristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 34 rev. pra for current information contact analog devices at (781) 937-1799 adsp-21992 august 2002 figure 20. serial port (sport) clocks and data drive edge drive edge sclk t ddten t ddtte sclk (int) sclk (ext) sclk fs drive edge sample edge data receive? external clock dxa/dxb t sclkw tdfse t hofse t sfse t hfse t sdre t hdre note: either the rising edge or falling edge of sclk (external), sclk (internal) can be used as the active sampling edge. dxa/dxb dxa/dxb sclk fs drive edge sample edge data receive? internal clock dxa/dxb t sclkiw t dfse t hofse t sfsi t hfsi t sdri t hdri sclk t ddtin t ddtti drive edge drive edge
preliminary technical data this information applies to a product under development. its charac teristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 35 rev. pra for current information contact analog devices at (781) 937-1799 adsp-21992 august 2002 serial port (sport) frame synch timing table 13 and figure 21 describe sport frame synch operations. to determine whether communication is po ssible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3) r/tclk width. table 13. serial port (sport) frame synch timing parameter description min max unit switching characteristics t hofse rfs hold after rclk (internally generated rfs) 1 1 referenced to drive edge. 12.4 ns t hofsi tfs hold after tclk (internally generated tfs) 1 12.2 ns t ddtenfs data enable from late fs or mce = 1, mfd = 0 2 2 mce = 1, tfs enable and tfs valid follow t ddtlfse and t ddtenfs . 4.7 ns t ddtlfse data delay from late external tfs or external rfs with mce = 1, mfd = 0 3 4.7 ns t hdte transmit data hold after tclk (external clk) 1 12.4 ns t hdti transmit data hold after tclk (internal clk) 1 0 12.2 ns t ddte transmit data delay after tclk (external clk) 1 0 12.2 ns t ddti transmit data delay after tclk (internal clk) 1 0 11.1 ns timing requirements t sfse tfs/rfs setup before tclk/rclk (external clk) 3 3 referenced to sample edge. ?0.6 tbd ns t sfsi tfs/rfs setup before tclk/rclk (internal clk) 3 ?0.6 tbd ns
preliminary technical data this information applies to a product under development. its charac teristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 36 rev. pra for current information contact analog devices at (781) 937-1799 adsp-21992 august 2002 figure 21. serial po rt (sport) frame synch drive sample drive first bit second bit sclk fs t hofse/i t ddtenfs t ddtlfse t sfse/i late external transmit fs external receive fs with mce = 1, mfd = 0 drive sample drive first bit second bit sclk fs t hofse/i t ddtenfs t ddtlfse dxa/dxb t sfse/i t ddte/i t hdte/i t ddte/i t hdte/i dxa/dxb
preliminary technical data this information applies to a product under development. its charac teristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 37 rev. pra for current information contact analog devices at (781) 937-1799 adsp-21992 august 2002 serial peripheral interfac e (spi) port?master timing table 14 and figure 22 describe spi port master operations. table 14. serial peripheral interface (spi) port?master timing parameter description min max unit switching characteristics t sdscim spiss low to first sclk edge 2t hclk ns t spichm serial clock high period 2t hclk ns t spiclm serial clock low period 2t hclk ns t sck serial clock period 4t hclk ns t hdsm last sclk edge to spiss high 2t hclk ns t spitdm sequential transfer delay 2t hclk ns t ddspid sclk edge to data out valid (data out delay) 0 6 ns t hdspid sclk edge to data out invalid (data out hold) 0 5 ns timing requirements t sspid data input valid to sclk edge (data input setup) 1.6 ns t hspid sclk sampling edge to data input invalid 1.6 ns
preliminary technical data this information applies to a product under development. its charac teristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 38 rev. pra for current information contact analog devices at (781) 937-1799 adsp-21992 august 2002 figure 22. serial peripheral interface (spi) port?master t sspid t hspid t hdspid lsb msb thspid t dds - pid mosi (output) miso (input) spiss (output) sclk (cpol = 0) (output) sclk (cpol = 1) (output) mosi (output) miso (input) cpha=1 cpha=0 t spichm t spiclm t spiclm t spiclk t spichm t hdsm t spitdm t hdspid lsb valid lsb msb msb valid thspid t dds - pid t sspid msb valid t sdscim t sspid lsb valid
preliminary technical data this information applies to a product under development. its charac teristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 39 rev. pra for current information contact analog devices at (781) 937-1799 adsp-21992 august 2002 serial peripheral interface (spi) port?slave timing table 15 and figure 23 describe spi port slave operations. table 15. serial peripheral interface (spi) port?slave timing parameter description min max unit switching characteristics t dsoe spiss assertion to data out active 06ns t dsdhi spiss deassertion to data high impedance 06ns t ddspid sclk edge to data out valid (data out delay) 0 5 ns t hdspid sclk edge to data out invalid (data out hold) 0 5 ns timing requirements t spichs serial clock high period 2t hclk ns t spicls serial clock low period 2t hclk ns t sck serial clock period 4t hclk ns t hds last sck edge to spiss not asserted 2t hclk ns t spitds sequential transfer delay 2t hclk ns t sdsci spiss assertion to first sck edge 2t hclk ns t sspid data input valid to sclk edge (data input setup) 1.6 ns t hspid sclk sampling edge to data input invalid 1.6 ns
preliminary technical data this information applies to a product under development. its charac teristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 40 rev. pra for current information contact analog devices at (781) 937-1799 adsp-21992 august 2002 figure 23. serial peripher al interface (spi) port?slave t hspid t ddspid t dsdhi lsb msb msb valid t hspid t dsoe t ddspid t hdspid miso (output) mosi (input) spiss (input) sclk (cpol = 0) (input) sclk (cpol = 1) (input) miso (output) mosi (input) cpha=1 cpha=0 tsspid t sdsci t spichs t spicls t spicls t spiclk t hds t spichs t sspid t hspid t dsdhi lsb valid msb msb valid t dsoe t ddspid t sspid lsb valid lsb tspitd s
preliminary technical data this information applies to a product under development. its charac teristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 41 rev. pra for current information contact analog devices at (781) 937-1799 adsp-21992 august 2002 jtag test and emulation port timing table 16 and figure 24 describe jtag port operations. table 16. jtag port timing parameter description min max unit switching characteristics t dtdo tdo delay from tck low 4 ns t dsys system outputs delay after tck low 1 1 system outputs = data15?0, addr21?0, ms3?0 , rd , wr , ack, clkout, bg , pf7?0, timexp, dt, dt1, tclk, tclk1, rclk, rclk1, tfs, tfs1, rfs, rfs1, bms . 05ns timing parameters t tck tck period 20 ns t stap tdi, tms setup before tck high 4 ns t htap tdi, tms hold after tck high 4 ns t ssys system inputs setu p before tck low 2 2 system inputs = da ta15?0, addr21?0, rd , wr , ack, br , bg , pf7?0, dr, dr1, tclk, tclk1, r clk, rclk1, tfs, tfs1, rfs, rfs1, clkin, reset . 4ns t hsys system inputs hold after tck low 2 5ns t trstw trst pulsewidth 3 3 50 mhz max. 4ns figure 24. jtag port timing tms tdi tdo system inputs system outputs tck t tck t htap t stap t dtdo t ssys t hsys t dsys
this information applies to a product under development. its charac teristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 42 rev. pra for current information contact analog devices at (781) 937-1799 adsp-21992 august 2002 preliminary technical data output drive currents figure 25 shows typical cu rrent and voltage characteristics for the output drivers of the adsp-21992. the curves represent the current drive capa bility of the output drivers as a function of output voltage. power dissipation total power dissipation has two components, one due to internal circuitry and one due to the switching of external output drivers. internal power dissipation is dependent on the instruction execu tion sequence and th e data operands involved. using the current specifications (i ddinpeak , i ddinhigh , i ddinlow , i ddidle ) from the electrical characteristics on page 22 and the current versus operation information in table 17 , designers can estimate the adsp-21992?s internal power supply (v ddint ) input current for a specific application, according to the formula in figure 26 . the external component of tota l power dissipation is caused by the switching of output pins. its magnitude depends on: ? the number of output pins th at switch during each cycle (o) ? the maximum frequency at wh ich they can switch (f) ? their load ca pacitance (c) ? their voltage swing (v dd ) and is calculated by the formula in figure 27 . the load capacitance should include the processor?s package capacitance (c in ). the switching frequency includes driving the load high and then back low. address and data pins can drive high and low at a maximum rate of 1 ? (2t ck ). the write strobe can switch every cycle at a frequency of 1 ? t ck . select pins switch at 1 ? (2t ck ), but selects can switch on each cycle. for example, estimate p ext with the following assumptions: ? a system with one bank of external data memory?asyn- chronous ram (16-bit) ? four 8k 16 ram chips are used, ea ch with a load of 10 pf ? external data memory writes occur every other cycle, a rate of 1 ? (4t ck ), with 50% of the pins switching ? the bus cycle time is 50 mhz (t ck = 20 ns) figure 25. adsp-21992 ty pical drive currents source (v ddext ) voltage ? v ?120 ?100 ?80 ?60 ?40 ?20 0 20 40 60 80 100 120 03.5 0.5 1 1.5 2.0 2.5 3.0 s o u r c e ( v d d e x t ) c u r r e n t ? m a tbd table 17. adsp-21992 operation types versus input current operation typical activity (i dd typical ) high activity (i dd idle ) low activity (i dd pwrdwn ) instruction type tbd tbd tbd instruction fetch tbd tbd tbd core memory access 1 tbd tbd tbd internal memory dma tbd tbd tbd external memory dma tbd tbd tbd data bit pattern for core memory access and dma tbd tbd tbd 1 these assume a 2:1 core clock ratio. for more information on ratios and clocks (t ck and t cclk ), see clock signals on page 13 . figure 26. i ddint calculation i ddint %typical i dd-typical () = %idle i dd-idle () %powerdown i dd-pwrdwn () ++ figure 27. p ext calculation p ext oc v dd 2 f =
this information applies to a product under development. its charac teristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 43 rev. pra for current information contact analog devices at (781) 937-1799 adsp-21992 august 2002 preliminary technical data the p ext equation is calculated fo r each class of pins that can drive as shown in table 18 . a typical power consumption can now be calculated for these conditions by adding a typical internal power dissipa- tion with the formula in figure 28 . where: ? p ext is from table 18 ? p int is i ddint 2.5v, using the calculation i ddint listed in power dissipation on page 42 note that the conditions causing a worst case p ext are different from those causing a worst case p int . maximum p int cannot occur while 100% of the output pins are switching from all ones to all zeros. note also that it is not common for an application to have 100% or even 50% of the outputs switchin g simultaneously. test conditions the dsp is tested for output en able, disable, and hold time. output disable time output pins are cons idered to be disabl ed when they stop driving, go into a high impedance state, and start to decay from their output high or lo w voltage. the time for the voltage on the bus to decay by ? v is dependent on the capacitive load, c l and the load current, i l . this decay time can be approximated by the equation in figure 29 . the output disable time t dis is the difference between t measured and t decay as shown in figure 30 . the time t measured is the interval from when the reference signal switches to when the output voltage deca ys ?v from the measured output high or output low voltage. the t decay is calculated with test loads c l and i l , and with ?v equal to 0.5 v. table 18. p ext calculation pin type # of pins % switching c f v dd 2 = p ext address 15 50 44.7 pf 12.5 mhz 10.9 v =0.046 w msx 10 44.7 pf 12.5 mhz 10.9 v =0.000 w wr 2 100 44.7 pf 25 mhz 10.9 v =0.024 w data 64 50 14.7 pf 12.5 mhz 10.9 v =0.064 w clkout 1 100 4.7 pf 25 mhz 10.9 v =0.001 w p ext =0.135 w figure 28. p total (typical) calculation figure 29. decay time calculation p total p = ext p int + t decay c l v ? i l --------------- = figure 30. output enable/disable figure 31. equivalent de vice loading for ac measurements (includes all fixtures) figure 32. voltage re ference levels for ac measurements (except ou tput enable/disable) reference signal t dis output starts driving v oh (measured) ? dv v ol (measured) + dv t measured v oh (measured) v ol (measured) 2.0v 1.0v high-impedance state. test conditions cause thisvolt- age to be approximately 1.5v output stops driving t decay t ena +1.5v 50pf to output pin iol ioh input or output 1.5v 1.5v
this information applies to a product under development. its charac teristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 44 rev. pra for current information contact analog devices at (781) 937-1799 adsp-21992 august 2002 preliminary technical data output enable time output pins are considered to be enabled when they have made a transition from a high impedance state to when they start driving. the output enable time t ena is the interval from when a reference signal reache s a high or low voltage level to when the output has reached a specified high or low trip point, as shown in the output enable/disable diagram ( figure 30 ). if multiple pins (such as the data bus) are enabled, the measurement value is that of the first pin to start driving. example system hold time calculation to determine the data output hold time in a particular system, first calculate t decay using the equation given in figure 29 . choose ?v to be th e difference between the adsp-21992?s output voltage and the input threshold for the device requiring th e hold time. a typical ?v will be 0.4 v. c l is the total bus capacitan ce (per data line), and i l is the total leakage or three state curr ent (per data line). the hold time will be t decay plus the minimum disable time (i.e., t datrwh for the write cycle). capacitive loading output delays and holds are based on standard capacitive loads: 50 pf on all pins (see figure 35 ). the delay and hold specifications given should be derated by a factor of 1.5 ns/50 pf for loads other than the nominal value of 50 pf. figure 33 and figure 34 show how output rise time varies with capacitance. these figures also show graphically how output delays and holds va ry with load capacitance. (note that this graph or derating does not apply to output disable delays; see output disable time on page 43 .) the graphs in these figu res may not be linear outside the ranges shown. environmental conditions the thermal characteristics in which the dsp is operating influence performance. thermal characteristics the adsp-21992 comes in a 196-lead ball grid array (mini-bga) package. the adsp -21992 is specified for an ambient temperature (t amb ) as calculated using the formula in figure 36 . to ensure that the t amb data sheet specification is not exceeded, a heatsink and/ or an air flow source may be used. a heatsink should be atta ched to the ground plane (as close as possible to the thermal pathways) with a thermal adhesive. figure 33. typical output rise time (10%?90%, v ddext =max) vs. load capacitance load capacitance?pf 16.0 8.0 0 0 200 20 40 60 80 100 120 140 160 180 14.0 12.0 4.0 2.0 10.0 6.0 tbd r i s e a n d f a l l t i m e s ? n s ( 0 . 3 5 v ? 3 . 1 2 v , 1 0 % ? 9 0 % ) figure 34. typical output rise time (10%-90%, v ddext =min) vs. load capacitance figure 35. typical output delay or hold vs. load capacitance (at max case temperature) figure 36. t case calculation 3.5 0 3.0 2.5 2.0 1.5 1.0 0.5 load capacitance?pf 0200 20 40 60 80 100 120 140 160 180 tbd r i s e a n d f a l l t i m e s ? n s ( 0 . 3 1 ? 2 . 8 2 , 1 0 % ? 9 0 % ) load capacitance?pf 5 ? 25 50 75 100 125 150 175 4 3 2 1 tbd o u t p u t d e l a y o r h o l d ? n s nominal t amb t case = pd ca ?
this information applies to a product under development. its charac teristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 45 rev. pra for current information contact analog devices at (781) 937-1799 adsp-21992 august 2002 preliminary technical data where: ? t amb = ambient temperature (m easured near top surface of package) ? pd = power dissipation in w (this value depends upon the specific application; a me thod for calculating pd is shown under power dissipation). ? ca = value from table 19 . ? jb = tbdc ? w there are some important thin gs to note about these t amb calculations and the values in table 19 : ? this represents thermal resistance at total power of tbd w. ? for the mini-bga package: jc = 8.4c ? w adsp-21992 pinout table 20 identifies the signal fo r each lqfp lead number. table 21 identifies the lqfp lead number for each signal name. table 5 describes each signal. table 19. ca va l u e s 1 1 these are preliminary estimates. airflow (linear ft. ? min.) 0 100 200 400 600 airflow (meters ? second) 00.5123 mini-bga: ca (c ? w) 26 24 22 20.9 19.8
this information applies to a product under development. its charac teristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 46 rev. pra for current information contact analog devices at (781) 937-1799 adsp-21992 august 2002 preliminary technical data table 20. 176-lead lqfp signal by lead number lead # signal lead # signal lead # signal lead # signal 1 n/c 45 vddext 89 n/c 133 vddext 2 n/c 46 a4 90 n/c 134 pf11 3 vddext 47 a3 91 vddext 135 pf10 4 rclk 48a2 92bypass 136pf9 5 sck 49 a1 93 bmode0 137 pf8 6 miso 50 a0 94 bmode1 138 pf7/spisel7 7 mosi 51 d15 95 bmode2 139 pf6/spisel6 8rd 52 d14 96 n/c 140 pf5/spisel5 9wr 53 d13 97 dgnd 141 pf4/spisel4 10 ack 54 d12 98 vddint 142 dgnd 11 br 55 d11 99 emu 143 vddext 12 bg 56 dgnd 100 trst 144 pf3/spisel3 13 bgh 57 vddext 101 tdo 145 pf2/spisel2 14 ioms 58 dgnd 102 tdi 146 pf1/spisel1 15 bms 59 vddint 103 tms 147 pf0/spiss0 16 ms3 60 d10 104 tck 148 dgnd 17 dgnd 61 d9 105 por 149 vddint 18 vddext 62 d8 106 reset 150 avss 19 ms2 63 d7 107 clkin 151 avdd 20 ms1 64 d6 108 xtal 152 n/c 21 ms0 65 d5 109 clkout 153 vref 22 dgnd 66 dgnd 110 convst 154 cml 23 vddint 67 vddint 111 tmr0 155 capt 24 a19 68 d4 112 dgnd 156 capb 25 a18 69 d3 113 vddext 157 sense 26 a17 70 d2 114 tmr1 158 vin3 27 a16 71 d1 115 tmr2 159 vin2 28 a15 72 d0 116 eis 160 vin1 29 a14 73 canrx 117 dgnd 161 vin0 30 a13 74 dgnd 118 vddint 162 ashan 31 dgnd 75 vddext 119 eiz 163 bshan 32 vddext 76 cl 120 eib 164 vin4 33 a12 77 ch 121 eia 165 vin5 34 a11 78 bl 122 auxtrip 166 vin6 35 a10 79 bh 123 aux1 167 vin7 36 a9 80 al 124 aux0 168 avss 37 a8 81 ah 125 pf15 169 avdd 38 a7 82 cantx 126 pf14 170 dt 39 a6 83 n/c 127 pf13 171 dr 40 a5 84 pwmsync 128 pf12 172 rfs 41 dgnd 85 pwmpol 129 dgnd 173 tfs 42 n/c 86 pwmsr 130 n/c 174 tclk 43 n/c 87 pwmtrip 131 n/c 175 dgnd 44 n/c 88 dgnd 132 n/c 176 n/c
this information applies to a product under development. its charac teristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 47 rev. pra for current information contact analog devices at (781) 937-1799 adsp-21992 august 2002 preliminary technical data table 21. 176-lead lqfp lead number by signal signal lead # signal lead # signal lead # signal lead # a0 50 capb 156 eis 116 pwmtrip 87 a1 49 capt 155 eiz 119 rclk 4 a10 35ch 77emu 99 rd 8 a11 34cl 76ioms 14 reset 106 a12 33 clkin 107 miso 6 rfs 172 a13 30 clkout 109 mosi 7 sck 5 a14 29 cml 154 ms0 21 sense 157 a15 28 convst 110 ms1 20 tck 104 a16 27d0 72ms2 19 tclk 174 a17 26d1 71ms3 16 tdi 102 a18 25 d10 60 n/c 1 tdo 101 a19 24 d11 55 n/c 2 tfs 173 a2 48 d12 54 n/c 42 tmr0 111 a3 47 d13 53 n/c 43 tmr1 114 a4 46 d14 52 n/c 44 tmr2 115 a5 40 d15 51 n/c 83 tms 103 a6 39 d2 70 n/c 89 trst 100 a7 38 d3 69 n/c 90 vddext 3 a8 37 d4 68 n/c 96 vddext 18 a9 36 d5 65 n/c 130 vddext 32 ack 10 d6 64 n/c 131 vddext 45 ah 81 d7 63 n/c 132 vddext 57 al 80 d8 62 n/c 152 vddext 75 ashan 162 d9 61 n/c 176 vddext 91 aux0 124 dgnd 17 pf0/spiss0 147 vddext 113 aux1 123 dgnd 22 pf1/spisel1 146 vddext 133 auxtrip 122 dgnd 31 pf10 135 vddext 143 avdd 151 dgnd 41 pf11 134 vddint 23 avdd 169 dgnd 56 pf12 128 vddint 59 avss 150 dgnd 58 pf13 127 vddint 67 avss 168 dgnd 66 pf14 126 vddint 98 bg 12 dgnd 74 pf15 125 vddint 118 bgh 13 dgnd 88 pf2/spisel2 145 vddint 149 bh 79 dgnd 97 pf3/spisel3 144 vin0 161 bl 78 dgnd 112 pf4/spisel4 141 vin1 160 bmode0 93 dgnd 117 pf5/spisel5 140 vin2 159 bmode1 94 dgnd 129 pf6/spisel6 139 vin3 158 bmode2 95 dgnd 142 pf7/spisel7 138 vin4 164 bms 15 dgnd 148 pf8 137 vin5 165 br 11 dgnd 175 pf9 136 vin6 166 bshan 163 dr 171 por 105 vin7 167 bypass 92 dt 170 pwmpol 85 vref 153 canrx 73 eia 121 pwmsr 86 wr 9 cantx 82 eib 120 pwmsync 84 xtal 108
this information applies to a product under development. its charac teristics and specifications are subject to change without n otice. analog devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 48 rev. pra for current information contact analog devices at (781) 937-1799 adsp-21992 august 2002 preliminary technical data outline dimensions dimensions in the outline diag ram are shown in millimeters. ordering guide 176-lead lqfp (st-176-1) part number ambient temperature range ins truction rate operating voltage package ADSP-21992YST ?40oc to +115oc 160 mhz 2 .5 int./3.3 ext. v 176-lead lqfp top view (pins down) pin 1 133 1 132 45 44 88 89 176 26.00 bsc sq 24.00 bsc sq 0.27 0.22 typ 0.17 0.50 bsc lead pitch 0.75 0.60 0.45 seating plane 1.60 max 0.15 0.05 0.08 max lead coplanarity 1.45 1.40 1.35 detail a notes: 1. dimensions in millimeters. 2. actual position of each lead is within 0.08 of its ideal position, when measured in the lateral direction. 3. center dimensions are nominal. detail a

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